d7 (reference) in projects: external - OpenGrok search results

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Searched refs:d7 (Results 1 – 25 of 451) sorted by relevance

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/external/tcpdump/tests/
D	pimv2-oobr-4.out	12 0x0000: 6900 1400 04d7 67b7 1400 0000 0400 0000 15 0x0030: 0200 6900 1400 04d7 67b7 1400 0000 0400 18 0x0060: 0000 0200 6900 1400 04d7 67b7 1400 0000 21 0x0090: 0000 0000 0200 6900 1400 04d7 67b7 1400 24 0x00c0: 0015 0000 0000 0200 6900 1400 04d7 67b7 27 0x00f0: 0001 0015 0000 0000 0200 6900 1400 04d7 31 0x0130: 04d7 67b7 1400 0000 0400 0000 0100 1500 34 0x0160: 1400 04d7 67b7 1400 0000 0400 0000 0100 37 0x0190: 6900 1400 04d7 67b7 1400 0000 0400 0000 40 0x01c0: 0200 6900 1400 04d7 67b7 1400 0000 0400 [all …]
/external/llvm/test/MC/ARM/
D	neon-bitwise-encoding.s	`169 vand d4, d7, d3 170 vand.8 d4, d7, d3 171 vand.16 d4, d7, d3 172 vand.32 d4, d7, d3 173 vand.64 d4, d7, d3 175 vand.i8 d4, d7, d3 176 vand.i16 d4, d7, d3 177 vand.i32 d4, d7, d3 178 vand.i64 d4, d7, d3 180 vand.s8 d4, d7, d3 [all …]`
D	neon-vld-encoding.s	`13 vld1.32 {d5, d6, d7}, [r3] 14 vld1.64 {d6, d7, d8}, [r3:64] 16 vld1.16 {d4, d5, d6, d7}, [r3:64] 17 vld1.32 {d5, d6, d7, d8}, [r3] 18 vld1.64 {d6, d7, d8, d9}, [r3:64] 40 vld1.32 {d5, d6, d7}, [r3]! 41 vld1.64 {d6, d7, d8}, [r3:64]! 45 vld1.32 {d5, d6, d7}, [r3], r6 46 vld1.64 {d6, d7, d8}, [r3:64], r6 49 vld1.16 {d4, d5, d6, d7}, [r3:64]! [all …]`
D	neon-mul-accum-encoding.s	`41 vqdmlal.s16 q11, d11, d7[0] 42 vqdmlal.s16 q11, d11, d7[1] 43 vqdmlal.s16 q11, d11, d7[2] 44 vqdmlal.s16 q11, d11, d7[3] 48 @ CHECK: vqdmlal.s16 q11, d11, d7[0] @ encoding: [0x47,0x63,0xdb,0xf2] 49 @ CHECK: vqdmlal.s16 q11, d11, d7[1] @ encoding: [0x4f,0x63,0xdb,0xf2] 50 @ CHECK: vqdmlal.s16 q11, d11, d7[2] @ encoding: [0x67,0x63,0xdb,0xf2] 51 @ CHECK: vqdmlal.s16 q11, d11, d7[3] @ encoding: [0x6f,0x63,0xdb,0xf2]`
/external/capstone/suite/MC/ARM/
D	neon-bitwise-encoding.s.cs	`46 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 47 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 48 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 49 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 50 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 51 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 52 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 53 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 54 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 55 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 [all …]`
D	neon-vld-encoding.s.cs	12 0x8f,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3] 13 0xdf,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64] 15 0x5f,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64] 16 0x8f,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3] 17 0xdf,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64] 36 0x8d,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]! 37 0xdd,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64]! 40 0x86,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3], r6 41 0xd6,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64], r6 43 0x5d,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]! [all …]
/external/libhevc/common/arm/
D	ihevc_inter_pred_chroma_vert_w16out.s	`191 vdup.32 d7,d6[1] 192 vld1.32 {d7[1]},[r6],r2 @loads pu1_src_tmp 193 vmull.u8 q2,d7,d1 @vmull_u8(vreinterpret_u8_u32(src_tmp2), coeffabs_1) 194 vdup.32 d7,d7[1] 195 vld1.32 {d7[1]},[r6],r2 197 vmlal.u8 q2,d7,d2 198 vdup.32 d7,d7[1] 199 vld1.32 {d7[1]},[r6] 201 vmlsl.u8 q2,d7,d3 238 vld1.8 {d7},[r6],r2 @load and increment [all …]`
D	ihevc_inter_pred_chroma_vert.s	`192 vdup.32 d7,d6[1] 193 vld1.32 {d7[1]},[r6],r2 @loads pu1_src_tmp 194 vmull.u8 q2,d7,d1 @vmull_u8(vreinterpret_u8_u32(src_tmp2), coeffabs_1) 195 vdup.32 d7,d7[1] 196 vld1.32 {d7[1]},[r6],r2 198 vmlal.u8 q2,d7,d2 199 vdup.32 d7,d7[1] 200 vld1.32 {d7[1]},[r6] 202 vmlsl.u8 q2,d7,d3 239 vld1.8 {d7},[r6],r2 @load and increment [all …]`
D	ihevc_intra_pred_luma_planar.s	`154 …vmov d7, d5 @mov #1 to d7 to used for inc for row+1 and dec for nt-1-r… 202 vadd.s8 d5, d5, d7 @(1) 204 vsub.s8 d6, d6, d7 @(1) 217 vadd.s8 d5, d5, d7 @(2) 218 vsub.s8 d6, d6, d7 @(2) 234 vadd.s8 d5, d5, d7 @(3) 235 vsub.s8 d6, d6, d7 @(3) 251 vadd.s8 d5, d5, d7 @(4) 252 vsub.s8 d6, d6, d7 @(4) 267 vadd.s8 d5, d5, d7 @(5) [all …]`
D	ihevc_itrans_recon_32x32.s	`122 @d5[0]= 50 d7[0]=18 123 @d5[1]= 46 d7[1]=13 124 @d5[2]= 43 d7[2]=9 125 @d5[3]= 38 d7[3]=4 178 vld1.16 {d4,d5,d6,d7},[r14]! 260 vmlsl.s16 q15,d14,d7[1] 265 vmlsl.s16 q14,d15,d7[1] 274 vmlal.s16 q8,d13,d7[2] 275 vmlal.s16 q9,d12,d7[0] 293 vmlsl.s16 q13,d9,d7[3] @// y1 * cos3 - y3 * sin1(part of b1) [all …]`
D	ihevc_padding.s	`146 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 147 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 148 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 149 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 150 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 265 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 266 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 267 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 268 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store 269 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store [all …]`
D	ihevc_itrans_recon_16x16.s	226 vld1.16 d7,[r9],r10 240 @d7=r3 248 vmlal.s16 q12,d7,d0[3] @// y1 * cos1 + y3 * cos3(part of b0) 249 vmlal.s16 q13,d7,d2[1] @// y1 * cos3 - y3 * sin1(part of b1) 250 vmlal.s16 q14,d7,d3[3] @// y1 * sin3 - y3 * cos1(part of b2) 251 vmlsl.s16 q15,d7,d2[3] @// y1 * sin1 - y3 * sin3(part of b3) 309 vld1.16 d7,[r9],r10 323 vmlal.s16 q12,d7,d2[3] @// y1 * cos1 + y3 * cos3(part of b0) 324 vmlsl.s16 q13,d7,d0[1] @// y1 * cos3 - y3 * sin1(part of b1) 325 vmlal.s16 q14,d7,d2[1] @// y1 * sin3 - y3 * cos1(part of b2) [all …]
D	ihevc_inter_pred_filters_luma_vert.s	173 vld1.u8 {d7},[r3],r2 @src_tmp4 = vld1_u8(pu1_src_tmp)@ 178 vmlsl.u8 q4,d7,d29 @mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)@ 198 vmlal.u8 q5,d7,d28 @mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)@ 214 vmlsl.u8 q6,d7,d27 228 vmlal.u8 q7,d7,d26 235 vld1.u8 {d7},[r3],r2 @src_tmp4 = vld1_u8(pu1_src_tmp)@ 266 vmlsl.u8 q4,d7,d29 @mul_res1 = vmlsl_u8(mul_res1, src_tmp4, coeffabs_7)@ 290 vmlal.u8 q5,d7,d28 @mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)@ 313 vmlsl.u8 q6,d7,d27 335 vmlal.u8 q7,d7,d26 [all …]
D	ihevc_itrans_recon_8x8.s	197 vld1.16 d7,[r9]! 206 vmlal.s16 q12,d7,d0[3] @// y1 * cos1 + y3 * cos3(part of b0) 208 vmlsl.s16 q13,d7,d1[3] @// y1 * cos3 - y3 * sin1(part of b1) 210 vmlsl.s16 q14,d7,d0[1] @// y1 * sin3 - y3 * cos1(part of b2) 212 vmlsl.s16 q15,d7,d1[1] @// y1 * sin1 - y3 * sin3(part of b3) 279 vqrshrn.s32 d7,q13,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct) 296 vld1.16 d7,[r9]! 313 vmlal.s16 q12,d7,d0[3] @// y1 * cos1 + y3 * cos3(part of b0) 314 vmlsl.s16 q13,d7,d1[3] @// y1 * cos3 - y3 * sin1(part of b1) 315 vmlsl.s16 q14,d7,d0[1] @// y1 * sin3 - y3 * cos1(part of b2) [all …]
D	ihevc_intra_pred_luma_mode_3_to_9.s	`206 vsub.s8 d7, d28, d6 @32-fract 213 vmull.u8 q12, d12, d7 @mul (row 0) 223 vmull.u8 q11, d16, d7 @mul (row 1) 234 vmull.u8 q10, d14, d7 @mul (row 2) 245 vmull.u8 q9, d10, d7 @mul (row 3) 256 vmull.u8 q12, d12, d7 @mul (row 4) 267 vmull.u8 q11, d16, d7 @mul (row 5) 278 vmull.u8 q10, d14, d7 @mul (row 6) 282 vmull.u8 q9, d10, d7 @mul (row 7) 333 vmull.u8 q10, d14, d7 @mul (row 6) [all …]`
D	ihevc_intra_pred_filters_luma_mode_11_to_17.s	`316 vsub.s8 d7, d28, d6 @32-fract 323 vmull.u8 q12, d12, d7 @mul (row 0) 333 vmull.u8 q11, d16, d7 @mul (row 1) 344 vmull.u8 q10, d14, d7 @mul (row 2) 355 vmull.u8 q9, d10, d7 @mul (row 3) 366 vmull.u8 q12, d12, d7 @mul (row 4) 377 vmull.u8 q11, d16, d7 @mul (row 5) 388 vmull.u8 q10, d14, d7 @mul (row 6) 392 vmull.u8 q9, d10, d7 @mul (row 7) 444 vmull.u8 q10, d14, d7 @mul (row 6) [all …]`
/external/valgrind/none/tests/arm/
D	neon64.c	646 TESTINSN_imm("vmov.i16 d7", d7, 0x700); in main() 661 TESTINSN_imm("vmvn.i16 d7", d7, 0x700); in main() 749 TESTINSN_bin("vorr d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); in main() 756 TESTINSN_bin("vorn d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); in main() 767 TESTINSN_bin("veor d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); in main() 778 TESTINSN_bin("vbsl d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); in main() 789 TESTINSN_bin("vbit d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); in main() 800 TESTINSN_bin("vbif d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff); in main() 898 TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); in main() 901 TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); in main() [all …]
/external/vixl/test/aarch32/
D	test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc	109 {{F32, d21, d26, d7}, false, al, "F32 d21 d26 d7", "F32_d21_d26_d7"}, 112 {{F32, d26, d1, d7}, false, al, "F32 d26 d1 d7", "F32_d26_d1_d7"}, 124 {{F32, d2, d7, d6}, false, al, "F32 d2 d7 d6", "F32_d2_d7_d6"}, 128 {{F32, d18, d7, d6}, false, al, "F32 d18 d7 d6", "F32_d18_d7_d6"}, 146 {{F32, d7, d3, d3}, false, al, "F32 d7 d3 d3", "F32_d7_d3_d3"}, 147 {{F32, d17, d7, d20}, false, al, "F32 d17 d7 d20", "F32_d17_d7_d20"}, 155 {{F32, d21, d31, d7}, false, al, "F32 d21 d31 d7", "F32_d21_d31_d7"}, 160 {{F32, d14, d12, d7}, false, al, "F32 d14 d12 d7", "F32_d14_d12_d7"}, 179 {{F32, d4, d7, d2}, false, al, "F32 d4 d7 d2", "F32_d4_d7_d2"}, 190 {{F32, d7, d6, d18}, false, al, "F32 d7 d6 d18", "F32_d7_d6_d18"}, [all …]
D	test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc	109 {{F32, d21, d26, d7}, false, al, "F32 d21 d26 d7", "F32_d21_d26_d7"}, 112 {{F32, d26, d1, d7}, false, al, "F32 d26 d1 d7", "F32_d26_d1_d7"}, 124 {{F32, d2, d7, d6}, false, al, "F32 d2 d7 d6", "F32_d2_d7_d6"}, 128 {{F32, d18, d7, d6}, false, al, "F32 d18 d7 d6", "F32_d18_d7_d6"}, 146 {{F32, d7, d3, d3}, false, al, "F32 d7 d3 d3", "F32_d7_d3_d3"}, 147 {{F32, d17, d7, d20}, false, al, "F32 d17 d7 d20", "F32_d17_d7_d20"}, 155 {{F32, d21, d31, d7}, false, al, "F32 d21 d31 d7", "F32_d21_d31_d7"}, 160 {{F32, d14, d12, d7}, false, al, "F32 d14 d12 d7", "F32_d14_d12_d7"}, 179 {{F32, d4, d7, d2}, false, al, "F32 d4 d7 d2", "F32_d4_d7_d2"}, 190 {{F32, d7, d6, d18}, false, al, "F32 d7 d6 d18", "F32_d7_d6_d18"}, [all …]
/external/pdfium/third_party/libpng16/arm/
D	filter_neon.S	`69 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] 73 vadd.u8 d3, d2, d7 93 vext.8 d7, d23, d23, #1 98 vadd.u8 d3, d2, d7 124 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] 133 vadd.u8 d3, d3, d7 159 vext.8 d7, d23, d23, #1 168 vadd.u8 d3, d3, d7 197 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] 207 vadd.u8 d3, d3, d7 [all …]`
/external/libpng/arm/
D	filter_neon.S	`69 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] 73 vadd.u8 d3, d2, d7 93 vext.8 d7, d23, d23, #1 98 vadd.u8 d3, d2, d7 124 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] 133 vadd.u8 d3, d3, d7 159 vext.8 d7, d23, d23, #1 168 vadd.u8 d3, d3, d7 197 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128] 207 vadd.u8 d3, d3, d7 [all …]`
/external/libavc/common/arm/
D	ih264_deblk_chroma_a9.s	`96 vld2.8 {d6, d7}, [r0], r1 @D6 = p1u , D7 = p1v 102 vaddl.u8 q5, d7, d1 @Q4,Q5 = q0 + p1 114 vmlal.u8 q14, d7, d31 @Q14,Q7 = (X2(p1U) + p0U + q1U) 179 vld4.16 {d1[0], d3[0], d5[0], d7[0]}, [r0], r1 180 vld4.16 {d1[1], d3[1], d5[1], d7[1]}, [r0], r1 181 vld4.16 {d1[2], d3[2], d5[2], d7[2]}, [r0], r1 182 vld4.16 {d1[3], d3[3], d5[3], d7[3]}, [r0], r1 192 vaddl.u8 q8, d3, d7 @(p0 + q1) 202 vmlal.u8 q10, d7, d31 @2*q1 + (p1 + q0) 218 vst4.16 {d1[0], d3[0], d5[0], d7[0]}, [r12], r1 [all …]`
/external/kernel-headers/original/uapi/linux/
D	uuid.h	`28 #define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ argument 33 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) 37 #define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ argument 38 GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7)`
/external/libmpeg2/common/arm/
D	impeg2_idct.s	`155 vld1.8 d7, [r2], r1 182 vaddw.u8 q11, q15, d7 186 vqmovun.s16 d7, q11 190 vst1.8 d7, [r3], r6 452 vld1.16 d7, [r9]! 461 vmlal.s16 q12, d7, d0[3] @// y1 * cos1 + y3 * cos3(part of b0) 463 vmlsl.s16 q13, d7, d1[3] @// y1 * cos3 - y3 * sin1(part of b1) 465 vmlsl.s16 q14, d7, d0[1] @// y1 * sin3 - y3 * cos1(part of b2) 467 vmlsl.s16 q15, d7, d1[1] @// y1 * sin1 - y3 * sin3(part of b3) 534 vqrshrn.s32 d7, q13, #idct_stg1_shift @// r3 = (a3 + b3 + rnd) >> 7(IDCT_STG1_SHIFT) [all …]`
/external/libavc/encoder/arm/
D	ime_distortion_metrics_a9q.s	`99 vld1.8 {d6, d7}, [r1], r3 103 vabdl.u8 q1, d7, d5 111 vld1.8 {d6, d7}, [r1], r3 115 vabal.u8 q1, d7, d5 181 vld1.8 {d6, d7}, [r1], r3 186 vabdl.u8 q1, d7, d5 194 vld1.8 {d6, d7}, [r1], r3 198 vabal.u8 q1, d7, d5 264 vld1.8 {d6, d7}, [r1], r3 270 vabdl.u8 q1, d7, d5 [all …]`

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