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Searched refs:data_addr (Results 1 – 20 of 20) sorted by relevance

/external/libusb/examples/
Dezusb.c248 uint32_t data_addr = 0; in parse_ihex() local
307 data_addr = off; in parse_ihex()
342 && (off != (data_addr + data_len) in parse_ihex()
346 external = is_external(data_addr, data_len); in parse_ihex()
347 rc = poke(context, data_addr, external, data, data_len); in parse_ihex()
350 data_addr = off; in parse_ihex()
368 external = is_external(data_addr, data_len); in parse_ihex()
369 rc = poke(context, data_addr, external, data, data_len); in parse_ihex()
396 uint32_t data_addr = 0; in parse_bin() local
406 external = is_external(data_addr, data_len); in parse_bin()
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/external/llvm/test/DebugInfo/Generic/
D2010-05-03-OriginDIE.ll14 %data_addr.i18 = alloca i64, align 8 ; <i64*> [#uses=1]
15 %data_addr.i17 = alloca i64, align 8 ; <i64*> [#uses=2]
16 %data_addr.i16 = alloca i64, align 8 ; <i64*> [#uses=0]
17 %data_addr.i15 = alloca i32, align 4 ; <i32*> [#uses=0]
18 %data_addr.i = alloca i64, align 8 ; <i64*> [#uses=0]
22 %a9 = load volatile i64, i64* %data_addr.i18, align 8 ; <i64> [#uses=1]
26 …call void @llvm.dbg.declare(metadata i64* %data_addr.i17, metadata !8, metadata !DIExpression()) n…
27 store i64 %a12, i64* %data_addr.i17, align 8
31 …call void @llvm.dbg.value(metadata i64* %data_addr.i17, i64 0, metadata !34, metadata !DIExpressio…
32 %a13 = load volatile i64, i64* %data_addr.i17, align 8 ; <i64> [#uses=1]
/external/swiftshader/third_party/LLVM/test/DebugInfo/
D2010-05-03-OriginDIE.ll14 %data_addr.i18 = alloca i64, align 8 ; <i64*> [#uses=1]
15 %data_addr.i17 = alloca i64, align 8 ; <i64*> [#uses=2]
16 %data_addr.i16 = alloca i64, align 8 ; <i64*> [#uses=0]
17 %data_addr.i15 = alloca i32, align 4 ; <i32*> [#uses=0]
18 %data_addr.i = alloca i64, align 8 ; <i64*> [#uses=0]
22 %a9 = volatile load i64* %data_addr.i18, align 8 ; <i64> [#uses=1]
26 call void @llvm.dbg.declare(metadata !{i64* %data_addr.i17}, metadata !8) nounwind, !dbg !14
27 store i64 %a12, i64* %data_addr.i17, align 8
31 call void @llvm.dbg.value(metadata !{i64* %data_addr.i17}, i64 0, metadata !34) nounwind
32 %a13 = volatile load i64* %data_addr.i17, align 8 ; <i64> [#uses=1]
/external/vixl/examples/aarch64/
Dsum-array.cc75 uintptr_t data_addr = reinterpret_cast<uintptr_t>(data); in main() local
76 simulator.WriteXRegister(0, data_addr); in main()
/external/valgrind/coregrind/m_debuginfo/
Ddebuginfo.c2022 Bool VG_(get_datasym_and_offset)( Addr data_addr, in VG_()
2028 data_addr, dname, in VG_()
3192 Addr data_addr, in data_address_is_in_var() argument
3218 data_addr, var->name ); in data_address_is_in_var()
3239 && res.word <= data_addr in data_address_is_in_var()
3240 && data_addr < res.word + var_szB) { in data_address_is_in_var()
3241 *offset = data_addr - res.word; in data_address_is_in_var()
3257 Addr data_addr, in format_message() argument
3319 data_addr, var_offset, vo_plural, var->name ); in format_message()
3328 data_addr, var_offset, vo_plural, var->name ); in format_message()
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/external/valgrind/include/
Dpub_tool_debuginfo.h130 extern Bool VG_(get_datasym_and_offset)( Addr data_addr,
150 Addr data_addr
/external/valgrind/helgrind/
Dhg_errors.c308 Addr data_addr; member
424 HG_(describe_addr) (xe->XE.Race.data_addr, &xe->XE.Race.data_addrinfo); in HG_()
432 Addr acc_addr = xe->XE.Race.data_addr; in HG_()
470 Addr data_addr, Int szB, Bool isWrite, in HG_()
485 VgSectKind sect = VG_(DebugInfo_sect_kind)( NULL, data_addr ); in HG_()
487 data_addr, VG_(pp_SectKind)(sect)); in HG_()
499 xe.XE.Race.data_addr = data_addr; in HG_()
527 XE_Race, data_addr, NULL, &xe ); in HG_()
674 ? xe1->XE.Race.data_addr == xe2->XE.Race.data_addr in HG_()
Dhg_addrdescr.h59 Addr data_addr );
Dhg_errors.h55 Addr data_addr, Int szB, Bool isWrite,
Dhg_main.c4355 Addr data_addr ) in HG_()
4367 data_addr - (UWord)(UInt)i * sizeof(UWord) ); in HG_()
4368 if (UNLIKELY(mm && addr_is_in_MM_Chunk(mm, data_addr))) in HG_()
4377 if (UNLIKELY(addr_is_in_MM_Chunk(mm, data_addr))) in HG_()
4387 tl_assert(addr_is_in_MM_Chunk(mm, data_addr)); in HG_()
/external/llvm/test/CodeGen/Thumb2/
Dmachine-licm.ll101 %data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; <i8> [#uses=2]
105 %1 = xor i8 %data_addr.013, %0 ; <i8> [#uses=1]
114 %8 = lshr i8 %data_addr.013, 1 ; <i8> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dmachine-licm.ll102 %data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; <i8> [#uses=2]
106 %1 = xor i8 %data_addr.013, %0 ; <i8> [#uses=1]
115 %8 = lshr i8 %data_addr.013, 1 ; <i8> [#uses=1]
/external/valgrind/callgrind/
Dsim.c1160 static void log_1I1Dr(InstrInfo* ii, Addr data_addr, Word data_size) in log_1I1Dr() argument
1166 DrRes = (*simulator.D1_Read)(data_addr, data_size); in log_1I1Dr()
1170 data_addr, data_size, cacheRes(DrRes)); in log_1I1Dr()
1196 static void log_0I1Dr(InstrInfo* ii, Addr data_addr, Word data_size) in log_0I1Dr() argument
1201 DrRes = (*simulator.D1_Read)(data_addr, data_size); in log_0I1Dr()
1204 data_addr, data_size, cacheRes(DrRes)); in log_0I1Dr()
1223 static void log_1I1Dw(InstrInfo* ii, Addr data_addr, Word data_size) in log_1I1Dw() argument
1229 DwRes = (*simulator.D1_Write)(data_addr, data_size); in log_1I1Dw()
1233 data_addr, data_size, cacheRes(DwRes)); in log_1I1Dw()
1256 static void log_0I1Dw(InstrInfo* ii, Addr data_addr, Word data_size) in log_0I1Dw() argument
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/external/valgrind/cachegrind/
Dcg_main.c385 void log_1IrNoX_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size) in log_1IrNoX_1Dr_cache_access() argument
394 cachesim_D1_doref(data_addr, data_size, in log_1IrNoX_1Dr_cache_access()
400 void log_1IrNoX_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size) in log_1IrNoX_1Dw_cache_access() argument
409 cachesim_D1_doref(data_addr, data_size, in log_1IrNoX_1Dw_cache_access()
418 void log_0Ir_1Dr_cache_access(InstrInfo* n, Addr data_addr, Word data_size) in log_0Ir_1Dr_cache_access() argument
422 cachesim_D1_doref(data_addr, data_size, in log_0Ir_1Dr_cache_access()
429 void log_0Ir_1Dw_cache_access(InstrInfo* n, Addr data_addr, Word data_size) in log_0Ir_1Dw_cache_access() argument
433 cachesim_D1_doref(data_addr, data_size, in log_0Ir_1Dw_cache_access()
/external/kernel-headers/original/uapi/linux/genwqe/
Dgenwqe_card.h338 __u64 data_addr; /* pointer to image data */ member
/external/valgrind/exp-bbv/tests/arm-linux/
Dll.S34 ldr r11,data_addr
426 data_addr: .word data_begin label
/external/syslinux/gpxe/src/drivers/net/
Dbnx2.c1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1465 fw.data_addr = bnx2_RXP_b06FwDataAddr; in bnx2_init_cpus()
1511 fw.data_addr = bnx2_TXP_b06FwDataAddr; in bnx2_init_cpus()
1557 fw.data_addr = bnx2_TPAT_b06FwDataAddr; in bnx2_init_cpus()
1603 fw.data_addr = bnx2_COM_b06FwDataAddr; in bnx2_init_cpus()
Dsky2.h2028 u32 data_addr; member
Dsky2.c928 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); in sky2_rx_submit()
937 re->data_addr = virt_to_bus(iob->data); in sky2_rx_map_iob()
Dbnx2.h4246 u32 data_addr; member