Searched refs:db_htile_surface (Results 1 – 7 of 7) sorted by relevance
2207 uint32_t db_htile_data_base, db_htile_surface; in si_init_depth_surface() local2287 db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface()2290 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_init_depth_surface()2310 db_htile_surface = 0; in si_init_depth_surface()2327 surf->db_htile_surface = db_htile_surface; in si_init_depth_surface()2645 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface); in si_emit_framebuffer_state()
351 unsigned db_htile_surface; member
1055 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | in r600_init_depth_surface()1527 if (a->rsurf && a->rsurf->db_htile_surface) { in r600_emit_db_state()1532 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in r600_emit_db_state()1577 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { in r600_emit_db_misc_state()
1249 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) | in evergreen_init_depth_surface()1720 if (a->rsurf && a->rsurf->db_htile_surface) { in evergreen_emit_db_state()1725 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in evergreen_emit_db_state()
1827 ds->db_htile_surface = S_028ABC_FULL_CACHE(1); in radv_initialise_ds_surface()1830 ds->db_htile_surface = 0; in radv_initialise_ds_surface()
1185 uint32_t db_htile_surface; member
702 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface); in radv_emit_fb_ds_state()