| /external/llvm/test/CodeGen/AArch64/ |
| D | fp16-v8-instructions.ll | 6 ; CHECK: fcvt
7 ; CHECK: fcvt
9 ; CHECK-DAG: fcvt
10 ; CHECK-DAG: fcvt
12 ; CHECK-DAG: fcvt
13 ; CHECK-DAG: fcvt
15 ; CHECK-DAG: fcvt
16 ; CHECK-DAG: fcvt
18 ; CHECK-DAG: fcvt
19 ; CHECK-DAG: fcvt
[all …]
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| D | fp16-v4-instructions.ll | 86 ; CHECK-DAG: fcvt
87 ; CHECK-DAG: fcvt
88 ; CHECK-DAG: fcvt
89 ; CHECK-DAG: fcvt
107 ; CHECK-DAG: fcvt
108 ; CHECK-DAG: fcvt
109 ; CHECK-DAG: fcvt
110 ; CHECK-DAG: fcvt
272 ; CHECK-DAG: fcvt
273 ; CHECK-DAG: fcvt
[all …]
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| D | f16-instructions.ll | 6 ; CHECK-NEXT: fcvt s1, h1
7 ; CHECK-NEXT: fcvt s0, h0
9 ; CHECK-NEXT: fcvt h0, s0
17 ; CHECK-NEXT: fcvt s1, h1
18 ; CHECK-NEXT: fcvt s0, h0
20 ; CHECK-NEXT: fcvt h0, s0
28 ; CHECK-NEXT: fcvt s1, h1
29 ; CHECK-NEXT: fcvt s0, h0
31 ; CHECK-NEXT: fcvt h0, s0
39 ; CHECK-NEXT: fcvt s1, h1
[all …]
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| D | f16-convert.ll | 6 ; CHECK-NEXT: fcvt s0, [[HREG]]
17 ; CHECK-NEXT: fcvt d0, [[HREG]]
28 ; CHECK-NEXT: fcvt s0, [[HREG]]
41 ; CHECK-NEXT: fcvt d0, [[HREG]]
54 ; CHECK-NEXT: fcvt s0, [[HREG]]
66 ; CHECK-NEXT: fcvt d0, [[HREG]]
78 ; CHECK-NEXT: fcvt s0, [[HREG]]
90 ; CHECK-NEXT: fcvt d0, [[HREG]]
102 ; CHECK-NEXT: fcvt s0, [[HREG]]
114 ; CHECK-NEXT: fcvt d0, [[HREG]]
[all …]
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| D | arm64-fast-isel-conversion-fallback.ll | 7 ; CHECK: fcvt s1, h0
18 ; CHECK: fcvt s1, h0
31 ; CHECK: fcvt h0, s0
42 ; CHECK: fcvt h0, s0
53 ; CHECK: fcvt h0, s0
63 ; CHECK: fcvt h0, s0
73 ; CHECK: fcvt h0, s0
84 ; CHECK: fcvt h0, s0
95 ; CHECK: fcvt h0, s0
106 ; CHECK: fcvt h0, s0
[all …]
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| D | floatdp_1source.ll | 115 ; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
119 ; CHECK: fcvt {{d[0-9]+}}, {{h[0-9]+}}
123 ; CHECK: fcvt {{h[0-9]+}}, {{s[0-9]+}}
127 ; CHECK: fcvt {{d[0-9]+}}, {{s[0-9]+}}
131 ; CHECK: fcvt {{h[0-9]+}}, {{d[0-9]+}}
135 ; CHECK: fcvt {{s[0-9]+}}, {{d[0-9]+}}
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| D | half.ll | 51 ; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
60 ; CHECK: fcvt {{d[0-9]+}}, {{h[0-9]+}}
69 ; CHECK: fcvt {{h[0-9]+}}, {{s[0-9]+}}
78 ; CHECK: fcvt {{h[0-9]+}}, {{d[0-9]+}}
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| D | postra-mi-sched.ll | 3 ; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the
4 ; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down
14 ; CHECK: fcvt
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| D | vector-fcopysign.ll | 20 ; CHECK-NEXT: fcvt s1, d1
36 ; CHECK-NEXT: fcvt d1, s1
98 ; CHECK-NEXT: fcvt s5, d1
102 ; CHECK-NEXT: fcvt s5, d2
105 ; CHECK-NEXT: fcvt s1, d1
108 ; CHECK-NEXT: fcvt s1, d1
|
| D | arm64-fcopysign.ll | 27 ; CHECK: fcvt d1, s1
39 ; CHECK: fcvt s0, d0
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| D | arm64-vcvt_f.ll | 67 ; CHECK: fcvt h[[HALFVAL:[0-9]+]], s0
76 ; CHECK: fcvt s0, {{h[0-9]+}}
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| D | arm64-vaargs.ll | 8 ; CHECK: fcvt
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| D | arm64-ccmp.ll | 610 ; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0
611 ; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1
613 ; CHECK-DAG: fcvt [[S2:s[0-9]+]], h2
614 ; CHECK-DAG: fcvt [[S3:s[0-9]+]], h3
628 ; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0
629 ; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1
631 ; CHECK-DAG: fcvt [[S2:s[0-9]+]], h2
632 ; CHECK-DAG: fcvt [[S3:s[0-9]+]], h3
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| D | arm64-fmax.ll | 62 ; CHECK: fcvt
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| D | arm64-fast-isel-conversion.ll | 187 ; CHECK: fcvt d0, s0
196 ; CHECK: fcvt s0, d0
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| D | arm64-vcvt.ll | 666 ;CHECK: fcvt
675 ;CHECK: fcvt
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-scalar-fp.txt | 199 # CHECK: fcvt h1, d2
200 # CHECK: fcvt s1, d2
201 # CHECK: fcvt d1, h2
202 # CHECK: fcvt s1, h2
203 # CHECK: fcvt d1, s2
204 # CHECK: fcvt h1, s2
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-fp-encoding.s | 240 fcvt h1, d2
241 fcvt s1, d2
242 fcvt d1, h2 define
243 fcvt s1, h2
244 fcvt d1, s2 define
245 fcvt h1, s2
247 ; CHECK: fcvt h1, d2 ; encoding: [0x41,0xc0,0x63,0x1e]
248 ; CHECK: fcvt s1, d2 ; encoding: [0x41,0x40,0x62,0x1e]
249 ; CHECK: fcvt d1, h2 ; encoding: [0x41,0xc0,0xe2,0x1e]
250 ; CHECK: fcvt s1, h2 ; encoding: [0x41,0x40,0xe2,0x1e]
[all …]
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| D | arm64-diagno-predicate.s | 5 fcvt d0, s0 define
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| D | basic-a64-instructions.s | 1831 fcvt d8, s9 define
1832 fcvt h10, s11
1858 fcvt s8, d9
1859 fcvt h10, d11
1881 fcvt s26, h27
1882 fcvt d28, h29
|
| /external/vixl/doc/ |
| D | changelog.md | 118 + Added support for double-to-float conversions using `fcvt`.
|
| /external/compiler-rt/lib/msan/ |
| D | msan_interceptors.cc | 642 INTERCEPTOR(char *, fcvt, double x, int a, int *b, int *c) { in INTERCEPTOR() argument
644 char *res = REAL(fcvt)(x, a, b, c); in INTERCEPTOR()
1551 INTERCEPT_FUNCTION(fcvt); in InitializeInterceptors()
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| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 707 0x28,0xc1,0x22,0x1e = fcvt d8, s9
708 0x6a,0xc1,0x23,0x1e = fcvt h10, s11
720 0x28,0x41,0x62,0x1e = fcvt s8, d9
721 0x6a,0xc1,0x63,0x1e = fcvt h10, d11
729 0x7a,0x43,0xe2,0x1e = fcvt s26, h27
730 0xbc,0xc3,0xe2,0x1e = fcvt d28, h29
|
| /external/pdfium/fxjs/ |
| D | cjs_publicmethods.cpp | 1088 strValue = fcvt(dValue, iDec, &iDec2, &iNegative); in AFPercent_Format()
1091 strValue = fcvt(dValue, iDec, &iDec2, &iNegative); in AFPercent_Format()
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 363 0x~~~~~~~~~~~~~~~~ 1ee2c304 fcvt d4, h24
364 0x~~~~~~~~~~~~~~~~ 1e22c04b fcvt d11, s2
365 0x~~~~~~~~~~~~~~~~ 1e63c128 fcvt h8, d9
366 0x~~~~~~~~~~~~~~~~ 1e23c02c fcvt h12, s1
367 0x~~~~~~~~~~~~~~~~ 1e6243ec fcvt s12, d31
368 0x~~~~~~~~~~~~~~~~ 1ee2433b fcvt s27, h25
|