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Searched refs:fmask (Results 1 – 25 of 44) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Dfp16instrinsmc.ll2 …ation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask
17 ; fmask: .ent foo1
18 ; fmask: .set noreorder
19 ; fmask: .set nomacro
20 ; fmask: .set noat
21 ; fmask: .set at
22 ; fmask: .set macro
23 ; fmask: .set reorder
24 ; fmask: .end foo1
38 ; fmask: .ent foo2
[all …]
Dtnaked.ll13 ; CHECK-NOT: .fmask {{.*}}
25 ; CHECK: .fmask 0x00000000,0
/external/mesa3d/src/amd/vulkan/
Dradv_image.c338 if (image->fmask.size) { in si_make_texture_descriptor()
343 va = gpu_address + image->offset + image->fmask.offset; in si_make_texture_descriptor()
370 S_008F1C_TILING_INDEX(image->fmask.tile_mode_index) | in si_make_texture_descriptor()
373 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1); in si_make_texture_descriptor()
462 struct radeon_surf fmask = image->surface; in radv_image_get_fmask_info() local
466 fmask.bo_alignment = 0; in radv_image_get_fmask_info()
467 fmask.bo_size = 0; in radv_image_get_fmask_info()
468 fmask.nsamples = 1; in radv_image_get_fmask_info()
469 fmask.flags |= RADEON_SURF_FMASK; in radv_image_get_fmask_info()
474 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE); in radv_image_get_fmask_info()
[all …]
Dradv_device.c1633 if (iview->image->fmask.size) { in radv_initialise_color_surface()
1634 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset; in radv_initialise_color_surface()
1636 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1); in radv_initialise_color_surface()
1637 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index); in radv_initialise_color_surface()
1639 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max); in radv_initialise_color_surface()
1692 if (iview->image->fmask.size) in radv_initialise_color_surface()
1716 if (!iview->image->fmask.size && in radv_initialise_color_surface()
/external/llvm/test/MC/Mips/
Dmips-pdr-bad.s29 .fmask # ASM: :[[@LINE]]:17: error: expected bitmask value
30 .fmask foo # ASM: :[[@LINE]]:20: error: bitmask not an absolute expression
31 .fmask 0x80000000 # ASM: :[[@LINE]]:27: error: unexpected token, expected comma
32 .fmask 0x80000000, # ASM: :[[@LINE]]:28: error: expected frame offset value
33 .fmask 0x80000000, foo # ASM: :[[@LINE]]:32: error: frame offset not an absolute expression
34 ….fmask 0x80000000, -4, bar # ASM: :[[@LINE]]:30: error: unexpected token, expected end of statement
Dmips-pdr.s14 # ASMOUT: .fmask 0x01010101,-8
48 .fmask 0x01010101,-8
58 .fmask 0x01010101,-8
Delf-tls.s26 .fmask 0x00000000,0
58 .fmask 0x00000000,0
90 .fmask 0x00000000,0
Dmips_gprel16.s25 .fmask 0x00000000,0
49 .fmask 0x00000000,0
Dxgot.s30 .fmask 0x00000000,0
Delf-N64.s28 .fmask 0x90000000,-4
Delf-gprel-32-64.s33 .fmask 0x00000000,0
Ddo_switch1.s21 .fmask 0x00000000,0
Dr-mips-got-disp.s21 .fmask 0x90000000,-4
Delf-relsym.s39 .fmask 0x00000000,0
Ddo_switch2.s20 .fmask 0x00000000,0
Ddo_switch3.s20 .fmask 0x00000000,0
Dmips_directives.s11 .fmask 0x00000000,0
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_texture.c477 assert(!rtex->fmask.size); in r600_degrade_tile_mode_to_linear()
589 struct radeon_surf fmask = {}; in r600_texture_get_fmask_info() local
599 fmask.bankw = rtex->surface.bankw; in r600_texture_get_fmask_info()
600 fmask.bankh = rtex->surface.bankh; in r600_texture_get_fmask_info()
601 fmask.mtilea = rtex->surface.mtilea; in r600_texture_get_fmask_info()
602 fmask.tile_split = rtex->surface.tile_split; in r600_texture_get_fmask_info()
605 fmask.bankh = 4; in r600_texture_get_fmask_info()
629 RADEON_SURF_MODE_2D, &fmask)) { in r600_texture_get_fmask_info()
634 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D); in r600_texture_get_fmask_info()
636 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64; in r600_texture_get_fmask_info()
[all …]
/external/ltp/testcases/kernel/syscalls/sched_setaffinity/
Dsched_setaffinity01.c51 static cpu_set_t *fmask = (void *)-1; variable
65 {&self_pid, &mask_size, &fmask, EFAULT},
/external/syslinux/gpxe/src/drivers/net/ath5k/
Dath5k_eeprom.c1586 unsigned int fmask, pmask; in ath5k_eeprom_read_ctl_info() local
1593 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1631 rep[j].freq = (val >> 8) & fmask; in ath5k_eeprom_read_ctl_info()
1632 rep[j + 1].freq = val & fmask; in ath5k_eeprom_read_ctl_info()
1643 rep[0].freq = (val >> 9) & fmask; in ath5k_eeprom_read_ctl_info()
1644 rep[1].freq = (val >> 2) & fmask; in ath5k_eeprom_read_ctl_info()
1645 rep[2].freq = (val << 5) & fmask; in ath5k_eeprom_read_ctl_info()
1649 rep[3].freq = (val >> 4) & fmask; in ath5k_eeprom_read_ctl_info()
1650 rep[4].freq = (val << 3) & fmask; in ath5k_eeprom_read_ctl_info()
1654 rep[5].freq = (val >> 6) & fmask; in ath5k_eeprom_read_ctl_info()
[all …]
/external/llvm/test/ExecutionEngine/RuntimeDyld/Mips/
DELF_Mips64r2N64_PIC_relocations.s33 .fmask 0x00000000,0
81 .fmask 0x00000000,0
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state.c2157 if (rtex->fmask.size) { in si_initialize_color_surface()
2159 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); in si_initialize_color_surface()
2187 if (!rtex->fmask.size && sctx->b.chip_class == SI) { in si_initialize_color_surface()
2428 if (rtex->fmask.size) { in si_set_framebuffer_state()
2557 if (tex->fmask.size) { in si_emit_framebuffer_state()
2559 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1); in si_emit_framebuffer_state()
2560 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index); in si_emit_framebuffer_state()
2561 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8; in si_emit_framebuffer_state()
2562 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max); in si_emit_framebuffer_state()
2974 if (tex->fmask.size) { in si_make_texture_descriptor()
[all …]
Dsi_blit.c434 } else if (rtex->fmask.size) { in si_blit_decompress_color()
490 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset) in si_decompress_sampler_color_textures()
517 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset) in si_decompress_image_color_textures()
698 if (tex->fmask.size == 0) in si_clear()
819 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) { in si_decompress_subresource()
/external/google-breakpad/src/common/android/
Dbreakpad_getcontext.S270 .fmask 0x00000000, 0
346 .fmask 0x00000000, 0
/external/mesa3d/src/gallium/drivers/r600/
Dr600_state.c953 if (rtex->fmask.size) { in r600_init_color_surface()
955 surf->cb_color_fmask = rtex->fmask.offset >> 8; in r600_init_color_surface()
956 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max); in r600_init_color_surface()
968 struct r600_fmask_info fmask; in r600_init_color_surface() local
971 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask); in r600_init_color_surface()
995 rctx->dummy_fmask->b.b.width0 < fmask.size || in r600_init_color_surface()
996 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) { in r600_init_color_surface()
1001 fmask.size, fmask.alignment); in r600_init_color_surface()
1010 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max); in r600_init_color_surface()
1124 if (rtex->fmask.size) { in r600_set_framebuffer_state()

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