/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
D | SystemZMCCodeEmitter.cpp | 52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 137 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in SystemZMCCodeEmitter 151 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDAddr12Encoding() 152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDAddr12Encoding() 161 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDAddr20Encoding() 162 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDAddr20Encoding() 171 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDXAddr12Encoding() 172 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDXAddr12Encoding() 173 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); in getBDXAddr12Encoding() 182 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDXAddr20Encoding() [all …]
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
D | PPCMCCodeEmitter.cpp | 96 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding() 169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding() 182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding() 195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding() 207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding() 221 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding() 225 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; in getMemRIEncoding() 240 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding() 244 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; in getMemRIXEncoding() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
D | PPCMCCodeEmitter.cpp | 55 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getDirectBrEncoding() 100 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getCondBrEncoding() 111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getHA16Encoding() 122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getLO16Encoding() 135 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16; in getMemRIEncoding() 139 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; in getMemRIEncoding() 153 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14; in getMemRIXEncoding() 157 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits; in getMemRIXEncoding() 177 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in PPCMCCodeEmitter
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMCodeEmitter.cpp | 150 unsigned getMachineOpValue(const MachineInstr &MI, 152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { in getMachineOpValue() function in __anon106cafd50111::ARMCodeEmitter 153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue() 439 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, in getMachineOpValue() function in ARMCodeEmitter 697 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi32immInstruction() 712 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi32immInstruction() 735 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi2piecesInstruction() 750 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi2piecesInstruction() 753 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; in emitMOVi2piecesInstruction() 777 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; in emitLEApcrelJTInstruction() [all …]
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsMCCodeEmitter.cpp | 560 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getUImm5Lsl2Encoding() 760 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in MipsMCCodeEmitter 786 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; in getMemEncoding() 787 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncoding() 801 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4() 803 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4() 815 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4Lsl1() 817 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4Lsl1() 829 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4Lsl2() 831 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4Lsl2() [all …]
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D | MipsMCCodeEmitter.h | 177 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCCodeEmitter.cpp | 60 unsigned getMachineOpValue(const MachineInstr &MI, 182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getDirectBrEncoding() 198 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getHA16Encoding() 207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getLO16Encoding() 218 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16; in getMemRIEncoding() 222 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits; in getMemRIEncoding() 234 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14; in getMemRIXEncoding() 238 return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits; in getMemRIXEncoding() 245 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, in getMachineOpValue() function in PPCCodeEmitter
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
D | SparcMCCodeEmitter.cpp | 57 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 106 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); in encodeInstruction() 116 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in SparcMCCodeEmitter 148 return getMachineOpValue(MI, MO, Fixups, STI); in getCallTargetOpValue() 183 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchTargetOpValue() 196 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchPredTargetOpValue() 208 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchOnRegTargetOpValue()
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | MipsCodeEmitter.cpp | 102 unsigned getMachineOpValue(const MachineInstr &MI, 163 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16; in getMemEncoding() 165 (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits; in getMemEncoding() 171 return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; in getSizeExtEncoding() 177 return getMachineOpValue(MI, MI.getOperand(OpNo-1)) + in getSizeInsEncoding() 178 getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; in getSizeInsEncoding() 183 unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI, in getMachineOpValue() function in MipsCodeEmitter
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/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiMCCodeEmitter.cpp | 58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp, 112 unsigned LanaiMCCodeEmitter::getMachineOpValue( in getMachineOpValue() function in llvm::__anonc3bb97680111::LanaiMCCodeEmitter 215 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); in getRiMemoryOpValue() 286 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); in getSplsOpValue() 296 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo); in getCallTargetOpValue() 309 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo); in getBranchTargetOpValue()
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
D | MBlazeMCCodeEmitter.cpp | 50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; 51 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const { in getMachineOpValue() function in __anon115f9e200111::MBlazeMCCodeEmitter 52 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue() 108 unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in MBlazeMCCodeEmitter
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
D | SIMCCodeEmitter.cpp | 59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 254 return getMachineOpValue(MI, MO, Fixups, STI); in getSOPPBrEncoding() 257 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in SIMCCodeEmitter
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D | R600MCCodeEmitter.cpp | 50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 155 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in R600MCCodeEmitter
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D | AMDGPUMCCodeEmitter.h | 35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function
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/external/llvm/lib/Target/BPF/MCTargetDesc/ |
D | BPFMCCodeEmitter.cpp | 50 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 76 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in BPFMCCodeEmitter
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonMCCodeEmitter.h | 63 unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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D | HexagonMCCodeEmitter.cpp | 792 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, in getMachineOpValue() function in HexagonMCCodeEmitter
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
D | AArch64MCCodeEmitter.cpp | 54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 186 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in AArch64MCCodeEmitter
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 402 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in ARMMCCodeEmitter
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 522 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in ARMMCCodeEmitter
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