Searched refs:getOpRegClass (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInsertWaits.cpp | 204 const TargetRegisterClass *RC = TII->getOpRegClass(MI, 0); in getHwCounts()
341 const TargetRegisterClass *RC = TII->getOpRegClass(*I, i); in pushInstruction()
471 const TargetRegisterClass *RC = TII->getOpRegClass(MI, i); in handleOperands()
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| D | SIInstrInfo.h | 410 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
430 return getOpRegClass(MI, OpNo)->getSize(); in getOpSize()
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| D | SIFixSGPRCopies.cpp | 344 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 240 EltSize = getOpRegClass(LdSt, 0)->getSize() / 2; in getMemOpBaseRegImmOfs()
244 EltSize = getOpRegClass(LdSt, Data0Idx)->getSize(); in getMemOpBaseRegImmOfs()
1847 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo
1870 return RI.hasVGPRs(getOpRegClass(MI, 0)); in canReadVGPR()
1872 return RI.hasVGPRs(getOpRegClass(MI, OpNo)); in canReadVGPR()
2248 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
2280 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands()
2949 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0); in getDestEquivalentVGPRClass()
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