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Searched refs:getOperand (Results 1 – 25 of 1030) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
DX86InstComments.cpp37 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
43 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
44 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
50 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
58 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
59 DecodePSHUFMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
281 MaskRegName = getRegName(MI->getOperand(1).getReg()); in getMaskName()
345 MaskRegName = getRegName(MI->getOperand(2).getReg()); in getMaskName()
384 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
389 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
391 MI->getOperand(NumOperands - 1).getImm(), in EmitAnyX86InstComments()
393 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
394 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
400 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
405 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
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/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp26 Constant *Op0 = C->getOperand(0); in CheapToScalarize()
28 if (C->getOperand(i) != Op0) in CheapToScalarize()
38 isa<ConstantInt>(I->getOperand(2))) in CheapToScalarize()
44 (CheapToScalarize(BO->getOperand(0), isConstant) || in CheapToScalarize()
45 CheapToScalarize(BO->getOperand(1), isConstant))) in CheapToScalarize()
49 (CheapToScalarize(CI->getOperand(0), isConstant) || in CheapToScalarize()
50 CheapToScalarize(CI->getOperand(1), isConstant))) in CheapToScalarize()
60 if (isa<ConstantAggregateZero>(SVI->getOperand(2))) in getShuffleMask()
62 if (isa<UndefValue>(SVI->getOperand(2))) in getShuffleMask()
66 const ConstantVector *CP = cast<ConstantVector>(SVI->getOperand(2)); in getShuffleMask()
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DInstCombineShifts.cpp23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); in commonShiftTransforms()
24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms()
92 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
95 return CanEvaluateTruncated(I->getOperand(0), Ty); in CanEvaluateShifted()
112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) && in CanEvaluateShifted()
113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC); in CanEvaluateShifted()
117 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
132 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
141 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
156 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
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/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp111 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
129 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
131 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
137 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
163 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
185 unsigned OldFMAReg = MI->getOperand(0).getReg(); in processBlock()
189 unsigned Reg2 = MI->getOperand(2).getReg(); in processBlock()
190 unsigned Reg3 = MI->getOperand(3).getReg(); in processBlock()
217 unsigned KilledProdReg = MI->getOperand(KilledProdOp).getReg(); in processBlock()
218 unsigned OtherProdReg = MI->getOperand(OtherProdOp).getReg(); in processBlock()
[all …]
DPPCISelDAGToDAG.cpp453 && isInt32Immediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
481 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) in isRotateAndMask()
514 SDValue Op0 = N->getOperand(0); in tryBitfieldInsert()
515 SDValue Op1 = N->getOperand(1); in tryBitfieldInsert()
535 if (Op0.getOperand(0).getOpcode() == ISD::SHL || in tryBitfieldInsert()
536 Op0.getOperand(0).getOpcode() == ISD::SRL) { in tryBitfieldInsert()
537 if (Op1.getOperand(0).getOpcode() != ISD::SHL && in tryBitfieldInsert()
538 Op1.getOperand(0).getOpcode() != ISD::SRL) { in tryBitfieldInsert()
545 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && in tryBitfieldInsert()
546 Op1.getOperand(0).getOpcode() != ISD::SRL) { in tryBitfieldInsert()
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp100 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
101 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
115 Base = Addr.getOperand(0); in SelectADDRdpii()
121 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) in SelectADDRdpii()
122 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRdpii()
125 Base = Addr.getOperand(0).getOperand(0); in SelectADDRdpii()
136 Base = Addr.getOperand(0); in SelectADDRcpii()
142 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) in SelectADDRcpii()
143 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRcpii()
146 Base = Addr.getOperand(0).getOperand(0); in SelectADDRcpii()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp60 const MCOperand &Dst = MI->getOperand(0); in printInst()
61 const MCOperand &MO1 = MI->getOperand(1); in printInst()
62 const MCOperand &MO2 = MI->getOperand(2); in printInst()
63 const MCOperand &MO3 = MI->getOperand(3); in printInst()
80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst()
104 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
115 MI->getOperand(3).getImm() == -4) { in printInst()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600ClauseMergePass.cpp77 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT)) in getCFAluSize()
84 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::Enabled)) in isCFAluEnabled()
101 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
126 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
127 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
128 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
129 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
130 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
142 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp525 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in tryIntrinsicChain()
593 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in tryIntrinsicNoChain()
605 SDValue Wrapper = N->getOperand(1); in SelectTexSurfHandle()
606 SDValue GlobalVal = Wrapper.getOperand(0); in SelectTexSurfHandle()
612 SDValue Src = N->getOperand(0); in SelectAddrSpaceCast()
734 SDValue Chain = N->getOperand(0); in tryLoad()
735 SDValue N1 = N->getOperand(1); in tryLoad()
916 SDValue Chain = N->getOperand(0); in tryLoadVector()
917 SDValue Op1 = N->getOperand(1); in tryLoadVector()
958 N->getOperand(N->getNumOperands() - 1))->getZExtValue(); in tryLoadVector()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst()
83 const MCOperand &MO3 = MI->getOperand(3); in printInst()
103 const MCOperand &Dst = MI->getOperand(0); in printInst()
104 const MCOperand &MO1 = MI->getOperand(1); in printInst()
105 const MCOperand &MO2 = MI->getOperand(2); in printInst()
130 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
144 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
145 MI->getOperand(3).getImm() == -4) { in printInst()
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/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp55 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
57 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
63 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
101 assert(InstIn.getOperand(2).isImm()); in LowerDins()
102 int64_t pos = InstIn.getOperand(2).getImm(); in LowerDins()
103 assert(InstIn.getOperand(3).isImm()); in LowerDins()
104 int64_t size = InstIn.getOperand(3).getImm(); in LowerDins()
110 InstIn.getOperand(2).setImm(pos - 32); in LowerDins()
116 InstIn.getOperand(3).setImm(size - 32); in LowerDins()
126 unsigned RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp100 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
101 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
102 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
114 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
115 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
126 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
127 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
136 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
145 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
146 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
[all …]
DHexagonMCDuplexInfo.cpp189 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
190 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
207 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
208 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
228 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
229 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
238 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
239 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
248 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
249 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
98 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
128 OutOps.push_back(Op.getOperand(0)); in SelectInlineAsmMemoryOperand()
164 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
165 N->getOperand(2) }; in Select()
171 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
172 N->getOperand(2) }; in Select()
178 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
179 N->getOperand(2), N->getOperand(3) }; in Select()
185 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); in selectMADD()
400 SDValue MultHi = ADDENode->getOperand(0); in selectMADD()
401 SDValue MultLo = ADDCNode->getOperand(0); in selectMADD()
432 ADDCNode->getOperand(1), in selectMADD()
433 ADDENode->getOperand(1)); in selectMADD()
439 MultNode->getOperand(0),// Factor 0 in selectMADD()
440 MultNode->getOperand(1),// Factor 1 in selectMADD()
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); in selectMSUB()
472 SDValue MultHi = SUBENode->getOperand(1); in selectMSUB()
473 SDValue MultLo = SUBCNode->getOperand(1); in selectMSUB()
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/external/llvm/unittests/IR/
DMDBuilderTest.cpp39 Metadata *Op = MD1->getOperand(0); in TEST_F()
53 EXPECT_TRUE(mdconst::hasa<ConstantInt>(R1->getOperand(0))); in TEST_F()
54 EXPECT_TRUE(mdconst::hasa<ConstantInt>(R1->getOperand(1))); in TEST_F()
55 ConstantInt *C0 = mdconst::extract<ConstantInt>(R1->getOperand(0)); in TEST_F()
56 ConstantInt *C1 = mdconst::extract<ConstantInt>(R1->getOperand(1)); in TEST_F()
67 EXPECT_EQ(R0->getOperand(0), R0); in TEST_F()
68 EXPECT_EQ(R1->getOperand(0), R1); in TEST_F()
69 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == nullptr); in TEST_F()
70 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == nullptr); in TEST_F()
78 EXPECT_TRUE(isa<MDString>(R0->getOperand(0))); in TEST_F()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp390 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) in isNegatibleForFree()
393 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); in isNegatibleForFree()
406 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) in isNegatibleForFree()
409 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); in isNegatibleForFree()
414 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); in isNegatibleForFree()
423 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
441 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) in GetNegatedExpression()
443 GetNegatedExpression(Op.getOperand(0), DAG, in GetNegatedExpression()
445 Op.getOperand(1)); in GetNegatedExpression()
448 GetNegatedExpression(Op.getOperand(1), DAG, in GetNegatedExpression()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUAsmPrinter.cpp64 const MachineOperand &MO = MI->getOperand(OpNo); in printOperand()
85 unsigned int value = MI->getOperand(OpNo).getImm(); in printU7ImmOperand()
93 char value = MI->getOperand(OpNo).getImm(); in printShufAddr()
103 O << (short) MI->getOperand(OpNo).getImm(); in printS16ImmOperand()
109 O << (unsigned short)MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
117 const MachineOperand &MO = MI->getOperand(OpNo); in printMemRegReg()
125 unsigned int value = MI->getOperand(OpNo).getImm(); in printU18ImmOperand()
133 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16) in printS10ImmOperand()
143 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16) in printU10ImmOperand()
152 assert(MI->getOperand(OpNo).isImm() && in printDFormAddr()
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/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp615 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
619 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
633 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
637 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
643 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, in isNegatibleForFree()
653 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
674 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, in GetNegatedExpression()
677 GetNegatedExpression(Op.getOperand(0), DAG, in GetNegatedExpression()
679 Op.getOperand(1), Flags); in GetNegatedExpression()
682 GetNegatedExpression(Op.getOperand(1), DAG, in GetNegatedExpression()
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp38 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
39 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
40 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
61 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
71 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
72 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
94 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
119 char Value = MI->getOperand(OpNo).getImm(); in printS5ImmOperand()
126 unsigned char Value = MI->getOperand(OpNo).getImm(); in printU5ImmOperand()
133 unsigned char Value = MI->getOperand(OpNo).getImm(); in printU6ImmOperand()
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/external/llvm/lib/Target/Lanai/InstPrinter/
DLanaiInstPrinter.cpp47 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
49 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
50 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
54 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
59 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
64 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
75 << getRegisterName(MI->getOperand(1).getReg()) << "], %" in printMemoryLoadIncrement()
76 << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
81 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) in printMemoryLoadIncrement()
82 << "], %" << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
[all …]
/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp47 isa<ConstantInt>(I->getOperand(2))) in cheapToScalarize()
53 (cheapToScalarize(BO->getOperand(0), isConstant) || in cheapToScalarize()
54 cheapToScalarize(BO->getOperand(1), isConstant))) in cheapToScalarize()
58 (cheapToScalarize(CI->getOperand(0), isConstant) || in cheapToScalarize()
59 cheapToScalarize(CI->getOperand(1), isConstant))) in cheapToScalarize()
113 unsigned opId = (B0->getOperand(0) == PN) ? 1 : 0; in scalarizePHI()
115 ExtractElementInst::Create(B0->getOperand(opId), Elt, in scalarizePHI()
116 B0->getOperand(opId)->getName() + ".Elt"), in scalarizePHI()
153 if (Constant *C = dyn_cast<Constant>(EI.getOperand(0))) in visitExtractElementInst()
159 if (ConstantInt *IdxC = dyn_cast<ConstantInt>(EI.getOperand(1))) { in visitExtractElementInst()
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/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp310 isInt32Immediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
356 SDValue N0 = N->getOperand(0); in PreprocessISelDAG()
357 SDValue N1 = N->getOperand(1); in PreprocessISelDAG()
384 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG()
406 Srl.getOperand(0), in PreprocessISelDAG()
503 ConstantSDNode *MulConst = dyn_cast<ConstantSDNode>(N.getOperand(1)); in canExtractShiftFromMul()
545 replaceDAGValue(N.getOperand(1), NewMulConst); in SelectImmShifterOperand()
560 BaseReg = N.getOperand(0); in SelectImmShifterOperand()
562 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)); in SelectImmShifterOperand()
584 BaseReg = N.getOperand(0); in SelectRegShifterOperand()
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