| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBankInfo.cpp | 35 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
46 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
58 const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID); in AArch64RegisterBankInfo()
94 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
108 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
110 return getRegBank(AArch64::CCRRegBankID); in getRegBankFromRegClass()
141 getRegBank(AArch64::GPRRegBankID)); in getInstrAlternativeMappings()
143 getRegBank(AArch64::FPRRegBankID)); in getInstrAlternativeMappings()
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| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 350 RegisterBank &getRegBank(unsigned ID) { in getRegBank() function
435 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() function
436 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); in getRegBank()
444 const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 48 const RegisterBank &RegBank = getRegBank(Idx); in verify()
60 RegisterBank &RegBank = getRegBank(ID); in createRegisterBank()
70 RegisterBank &RB = getRegBank(ID); in addRegBankCoverage()
106 recordRegBankForType(getRegBank(ID), SVT); in addRegBankCoverage()
169 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, in getRegBank() function in RegisterBankInfo
235 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
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| D | RegBankSelect.cpp | 93 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
161 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenTarget.cpp | 161 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
175 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); in getRegisterByName()
185 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
187 ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses(); in getRegisterVTs()
204 ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses(); in ReadLegalValueTypes()
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| D | CodeGenTarget.h | 99 CodeGenRegBank &getRegBank() const;
111 return *getRegBank().getRegClass(R); in getRegisterClass()
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| D | DAGISelMatcherGen.cpp | 28 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
29 ArrayRef<CodeGenRegisterClass*> RCs = T.getRegBank().getRegClasses(); in getRegisterValueType()
586 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
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| D | RegisterInfoEmitter.cpp | 362 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); in runMCDesc()
842 CodeGenRegBank &RegBank = Target.getRegBank(); in run()
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| D | FastISelEmitter.cpp | 256 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); in initialize()
412 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); in PhyRegForNode()
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| D | AsmWriterEmitter.cpp | 520 Target.getRegBank().getRegisters(); in EmitGetRegisterName()
707 Target.getRegBank().getRegClasses(); in EmitRegIsInRegClass()
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| D | AsmMatcherEmitter.cpp | 916 Target.getRegBank().getRegisters(); in BuildRegisterClasses()
918 Target.getRegBank().getRegClasses(); in BuildRegisterClasses()
1785 Target.getRegBank().getRegisters(); in EmitMatchRegisterName()
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| D | CodeGenInstruction.cpp | 442 .contains(T.getRegBank().getReg(ADI->getDef()))) in tryAliasOpMatch()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 221 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
235 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName()
244 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
246 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
261 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
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| D | CodeGenTarget.h | 114 CodeGenRegBank &getRegBank() const;
126 return *getRegBank().getRegClass(R); in getRegisterClass()
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| D | DAGISelMatcherGen.cpp | 28 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
619 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
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| D | FastISelEmitter.cpp | 263 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); in initialize()
436 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); in PhyRegForNode()
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| D | AsmMatcherEmitter.cpp | 1203 const auto &Registers = Target.getRegBank().getRegisters(); in buildRegisterClasses()
1204 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()
2337 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterName()
2360 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterAltName()
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| D | RegisterInfoEmitter.cpp | 1013 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); in runMCDesc()
1527 CodeGenRegBank &RegBank = Target.getRegBank(); in run()
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| D | CodeGenInstruction.cpp | 489 .contains(T.getRegBank().getReg(ADI->getDef()))) in tryAliasOpMatch()
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| D | AsmWriterEmitter.cpp | 550 const auto &Registers = Target.getRegBank().getRegisters(); in EmitGetRegisterName()
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 162 const RegisterBank *getRegBank(const MachineFunction &MF, StringRef Name);
380 const auto *RegBank = getRegBank(MF, VReg.Class.Value); in initializeRegisterInfo()
736 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks()
751 const RegisterBank *MIRParserImpl::getRegBank(const MachineFunction &MF, in getRegBank() function in MIRParserImpl
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