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Searched refs:getRegClass (Results 1 – 25 of 202) sorted by relevance

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/external/llvm/lib/Target/Mips/
DMipsOptionRecord.h46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
53 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
54 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
137 MRI.getRegClass(SrcReg) : in getCopyRegClasses()
145 MRI.getRegClass(DstReg) : in getCopyRegClasses()
183 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
276 if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) in runOnMachineFunction()
319 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) { in runOnMachineFunction()
357 DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
358 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
359 Src1RC = MRI.getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
DSILowerI1Copies.cpp86 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in runOnMachineFunction()
102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction()
103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction()
DSIInstrInfo.cpp336 const TargetRegisterClass *DstRC = MRI.getRegClass(FirstDst->getReg()); in shouldClusterMemOps()
1246 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) in FoldImmediate()
1249 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
1293 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) in FoldImmediate()
1296 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) in FoldImmediate()
1548 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize(); in isImmOperandLegal()
1588 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); in usesConstantBus()
1685 RI.getRegClass(RegClass)->getSize())) { in verifyInstruction()
1713 const TargetRegisterClass *RC = RI.getRegClass(RegClass); in verifyInstruction()
1856 return MRI.getRegClass(Reg); in getOpRegClass()
[all …]
DSIRegisterInfo.h99 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
105 RC = MRI.getRegClass(Reg); in isSGPRReg()
DSIFoldOperands.cpp212 MRI.getRegClass(UseReg) : in foldOperand()
219 TRI.getRegClass(FoldDesc.OpInfo[0].RegClass); in foldOperand()
240 MRI.getRegClass(DestReg) : in foldOperand()
/external/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.cpp239 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) { in printRegOperand()
242 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) { in printRegOperand()
245 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) { in printRegOperand()
248 } else if (MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(reg)) { in printRegOperand()
251 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) { in printRegOperand()
254 } else if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(reg)) { in printRegOperand()
257 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) { in printRegOperand()
260 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) { in printRegOperand()
263 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) { in printRegOperand()
266 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) { in printRegOperand()
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/external/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp37 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
48 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) && in AArch64RegisterBankInfo()
50 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) && in AArch64RegisterBankInfo()
60 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) && in AArch64RegisterBankInfo()
DAArch64AdvSIMDScalarPass.cpp117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
DRegisterBankInfo.cpp78 else if (RB.covers(*TRI.getRegClass(RCId))) in addRegBankCoverage()
93 const TargetRegisterClass &CurRC = *TRI.getRegClass(RCId); in addRegBankCoverage()
116 DEBUG(dbgs() << TRI.getRegClassName(TRI.getRegClass(SubRCId)) << ", "); in addRegBankCoverage()
141 const TargetRegisterClass *SubRC = TRI.getRegClass(SubRCId); in addRegBankCoverage()
378 RC = MRI.getRegClass(Reg); in getSizeInBits()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp64 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in MaybeRewriteToDrop()
91 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); in MaybeRewriteToFallthrough()
159 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
DWebAssemblyRegColoring.cpp139 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC) in runOnMachineFunction()
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp142 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
279 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
280 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
531 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
532 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
548 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
554 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
658 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp131 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
132 MRI.getRegClass(AddendSrcReg)) in processBlock()
137 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
237 MRI.getRegClass(OldFMAReg))) in processBlock()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
162 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
251 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); in AddRegisterOperand()
446 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
503 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
554 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
595 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
612 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); in EmitCopyFromReg()
142 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
199 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI); in CreateVirtualRegisters()
217 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
296 DstRC = TII->getRegClass(*II, IIOpNum, TRI); in AddRegisterOperand()
402 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
509 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
549 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); in EmitCopyToRegClassNode()
566 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence()
579 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterCoalescer.cpp273 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); in setRegisters()
276 } else if (!MRI.getRegClass(Src)->contains(Dst)) { in setRegisters()
289 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters()
290 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters()
306 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters()
307 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters()
717 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) in RemoveCopyByCommutingDef()
826 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI); in ReMaterializeTrivialDef()
828 if (MRI->getRegClass(DstReg) != RC) in ReMaterializeTrivialDef()
1086 const TargetRegisterClass *RC = MRI->getRegClass(CP.getSrcReg()); in shouldJoinPhys()
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/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp428 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
439 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
525 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
624 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource()
684 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); in findNextSource()
719 const TargetRegisterClass *NewRC = MRI->getRegClass(SrcRegs[0].Reg); in insertPHI()
938 const TargetRegisterClass *DefRC = MRI.getRegClass(Def.Reg); in RewriteSource()
1410 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg)) in foldRedundantCopy()
1801 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) || in getNextSourceFromInsertSubreg()
DDetectDeadLanes.cpp161 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy()
257 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
376 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes()
441 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
490 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput()
DRegAllocBase.cpp103 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
128 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
/external/llvm/lib/Target/Hexagon/
DHexagonGenPredicate.cpp113 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
316 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
415 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
460 if (MRI->getRegClass(DR.R) != PredRC) in eliminatePredCopies()
462 if (MRI->getRegClass(SR.R) != PredRC) in eliminatePredCopies()
DHexagonSplitDouble.cpp206 if (MRI->getRegClass(R) == DoubleRC) in partitionRegisters()
244 if (MRI->getRegClass(T) != DoubleRC) in partitionRegisters()
457 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass); in collectIndRegsForLoop()
471 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC) in collectIndRegsForLoop()
473 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC) in collectIndRegsForLoop()
492 if (MRI->getRegClass(R) == DoubleRC) in collectIndRegsForLoop()
564 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) { in createHalfInstr()
631 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg()); in splitMemRef()
966 if (MRI->getRegClass(DstR) == DoubleRC) { in splitInstr()
1072 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg()) in collapseRegPairs()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() function in TargetInstrInfo
45 return TRI->getRegClass(RegClass); in getRegClass()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelDAGToDAG.cpp157 TII.getRegClass(DefMCID, UI.getUse().getResNo(), TRI); in FixRegisterClasses()
163 TII.getRegClass(UseMCID, UseMCID.getNumDefs()+UI.getOperandNo(), TRI); in FixRegisterClasses()

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