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Searched refs:hasVGPRs (Results 1 – 6 of 6) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
319 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) { in runOnMachineFunction()
344 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction()
361 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
DSIRegisterInfo.h94 return !hasVGPRs(RC); in isSGPRClass()
112 bool hasVGPRs(const TargetRegisterClass *RC) const;
DSIShrinkInstructions.cpp75 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg())); in isVGPR()
77 return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg())); in isVGPR()
DSIInstrInfo.cpp620 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); in storeRegToStackSlot()
714 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); in loadRegFromStackSlot()
1870 return RI.hasVGPRs(getOpRegClass(MI, 0)); in canReadVGPR()
1872 return RI.hasVGPRs(getOpRegClass(MI, OpNo)); in canReadVGPR()
2238 if (RI.hasVGPRs(OpRC)) { in legalizeOperands()
2281 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()
2959 if (RI.hasVGPRs(NewDstRC)) in getDestEquivalentVGPRClass()
DSIRegisterInfo.cpp708 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs() function in SIRegisterInfo
1013 return hasVGPRs(RC); in isVGPR()
DSIWholeQuadMode.cpp184 TRI->hasVGPRs(TRI->getPhysRegClass(Reg))) { in scanInstructions()