Searched refs:hwreg (Results 1 – 10 of 10) sorted by relevance
/external/llvm/test/MC/AMDGPU/ |
D | sopk.s | 82 s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31) 87 s_getreg_b32 s2, hwreg(51, 1, 31) 92 s_getreg_b32 s2, hwreg(51) 112 s_setreg_b32 hwreg(HW_REG_HW_ID), s2 117 s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2 122 s_setreg_b32 hwreg(5, 1, 31), s2 132 s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff
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D | sopk-err.s | 8 s_setreg_b32 hwreg(0x40), s2 11 s_setreg_b32 hwreg(HW_REG_WRONG), s2 14 s_setreg_b32 hwreg(3,32,32), s2 17 s_setreg_b32 hwreg(3,0,33), s2 23 s_setreg_imm32_b32 hwreg(3,0,33), 0xff 26 s_getreg_b32 s2, hwreg(3,32,32)
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | sopk_vi.txt | 51 # VI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x82,0xb8] 54 # VI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8] 57 # VI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8] 60 # VI: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9] 63 # VI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0x…
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/external/llvm/test/CodeGen/AMDGPU/ |
D | llvm.amdgcn.s.getreg.ll | 6 ; CHECK: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_LDS_ALLOC, 8, 23)
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/external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
D | radeon_compiler_regalloc_tests.c | 36 void (*allocate)(void * data, unsigned input, unsigned hwreg), in dummy_allocate_hw_inputs() argument
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
D | radeon_compiler.h | 124 void (*allocate)(void * data, unsigned input, unsigned hwreg),
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D | radeon_pair_regalloc.c | 255 unsigned int hwreg) in alloc_input_simple() argument 264 s->Input[input].Index = hwreg; in alloc_input_simple()
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/external/mesa3d/src/gallium/drivers/r300/ |
D | r300_fs.c | 116 void (*allocate)(void * data, unsigned input, unsigned hwreg), in allocate_hardware_inputs() argument
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstructions.td | 405 (ins hwreg:$simm16), " $sdst, $simm16" 411 (ins SReg_32:$sdst, hwreg:$simm16), " $simm16, $sdst" 417 (ins i32imm:$imm, hwreg:$simm16), " $simm16, $imm"
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D | SIInstrInfo.td | 573 def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
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