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Searched refs:iPTR (Results 1 – 25 of 66) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenDAGISel.inc34 …// Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
35 // Dst: (VMOVNTPSmr addr:iPTR:$dst, VR128:v4f32:$src)
39 …// Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
40 // Dst: (VMOVNTDQmr addr:iPTR:$dst, VR128:v4f32:$src)
48 …// Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
49 // Dst: (MOVNTPSmr addr:iPTR:$dst, VR128:v4f32:$src)
56 …// Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
57 // Dst: (MOVNTDQmr addr:iPTR:$dst, VR128:v4f32:$src)
70 …// Src: (st VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity …
71 // Dst: (VMOVNTPDmr addr:iPTR:$dst, VR128:v2f64:$src)
[all …]
DX86InstrMMX.td196 (iPTR 0))))))]>;
398 (iPTR imm:$src2)))]>;
405 GR32:$src2, (iPTR imm:$src3)))]>;
413 (iPTR imm:$src3)))]>;
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUOperands.td578 def calltarget : Operand<iPTR> {
584 def relcalltarget : Operand<iPTR> {
600 def indcalltarget : Operand<iPTR> {
618 def shufaddr : Operand<iPTR> {
624 def dformaddr : Operand<iPTR> {
632 def addr256k : Operand<iPTR> {
638 def memri18 : Operand<iPTR> {
644 def memrr : Operand<iPTR> {
657 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr",
659 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr",
[all …]
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInfo.td28 def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
30 SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td443 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
451 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
461 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
469 (iPTR imm)),
580 (iPTR imm)))]>,
587 (From.VT From.RC:$src1), (iPTR imm))),
603 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
613 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
622 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
633 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
[all …]
DX86InstrSSE.td333 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
335 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td39 def tocentry : Operand<iPTR> {
1123 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1125 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1127 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1129 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1132 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1134 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1136 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1138 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
DPPCInstrInfo.td65 def tocentry32 : Operand<iPTR> {
622 def calltarget : Operand<iPTR> {
627 def abscalltarget : Operand<iPTR> {
646 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
653 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
661 def dispRI : Operand<iPTR> {
668 def dispRIX : Operand<iPTR> {
675 def dispRIX16 : Operand<iPTR> {
682 def dispSPE8 : Operand<iPTR> {
689 def dispSPE4 : Operand<iPTR> {
[all …]
/external/swiftshader/third_party/LLVM/utils/TableGen/
DDAGISelMatcher.cpp346 if (T1 == MVT::iPTR) in TypesAreContradictory()
349 if (T2 == MVT::iPTR) in TypesAreContradictory()
DCodeGenDAGPatterns.cpp50 assert((VT < MVT::LAST_VALUETYPE || VT == MVT::iPTR || in TypeSet()
161 case MVT::iPTR: in MergeInTypeInfo()
183 if ((InVT.TypeVec[0] == MVT::iPTR || InVT.TypeVec[0] == MVT::iPTRAny) && in MergeInTypeInfo()
189 if ((InVT.TypeVec[0] == MVT::iPTR || InVT.TypeVec[0] == MVT::iPTRAny) && in MergeInTypeInfo()
848 return NodeToApply->UpdateNodeType(ResNo, MVT::iPTR, TP); in ApplyTypeConstraint()
988 return MVT::iPTR; in getKnownType()
1298 return EEVT::TypeSet(MVT::iPTR, TP); in getImplicitType()
1404 if (VT == MVT::iPTR || VT == MVT::iPTRAny) in ApplyTypeConstraints()
1494 MadeChange |= getChild(0)->UpdateNodeType(0, MVT::iPTR, TP); in ApplyTypeConstraints()
1536 MadeChange |= UpdateNodeType(ResNo, MVT::iPTR, TP); in ApplyTypeConstraints()
[all …]
DCodeGenTarget.cpp43 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
91 case MVT::iPTR: return "MVT::iPTR"; in getEnumName()
DCodeGenDAGPatterns.h68 assert(T < MVT::LAST_VALUETYPE || T == MVT::iPTR || T == MVT::iPTRAny); in isConcrete()
78 return getConcrete() == MVT::iPTR || getConcrete() == MVT::iPTRAny; in isDynamicallyResolved()
/external/llvm/utils/TableGen/
DDAGISelMatcher.cpp316 if (T1 == MVT::iPTR) in TypesAreContradictory()
319 if (T2 == MVT::iPTR) in TypesAreContradictory()
DCodeGenTarget.cpp45 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
126 case MVT::iPTR: return "MVT::iPTR"; in getEnumName()
DCodeGenDAGPatterns.cpp56 assert((VT < MVT::LAST_VALUETYPE || VT == MVT::iPTR || in TypeSet()
168 case MVT::iPTR: in MergeInTypeInfo()
190 if ((InVT.TypeVec[0] == MVT::iPTR || InVT.TypeVec[0] == MVT::iPTRAny) && in MergeInTypeInfo()
196 if ((InVT.TypeVec[0] == MVT::iPTR || InVT.TypeVec[0] == MVT::iPTRAny) && in MergeInTypeInfo()
1002 return NodeToApply->UpdateNodeType(ResNo, MVT::iPTR, TP); in ApplyTypeConstraint()
1113 return UpdateNodeType(ResNo, MVT::iPTR, TP); in UpdateNodeTypeFromInst()
1197 return MVT::iPTR; in getKnownType()
1564 return EEVT::TypeSet(MVT::iPTR, TP); in getImplicitType()
1725 if (VT == MVT::iPTR || VT == MVT::iPTRAny) in ApplyTypeConstraints()
1792 MadeChange |= getChild(0)->UpdateNodeType(0, MVT::iPTR, TP); in ApplyTypeConstraints()
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td19 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
20 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td48 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
49 SDTCisVT<0, iPTR>]>
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h122 iPTR = 255, enumerator
244 case iPTR: in getSizeInBits()
DValueTypes.td79 def iPTR : ValueType<0 , 255>;
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h172 iPTR = 126, enumerator
435 case iPTR: in getSizeInBits()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td94 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
95 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
108 def MEMrr : Operand<iPTR> {
113 def MEMri : Operand<iPTR> {
119 def TLSSym : Operand<iPTR>;
225 def getPCX : Operand<iPTR> {
701 [(set iPTR:$dst, ADDRri:$addr)]>;
1521 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1532 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1629 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
[all …]
DSparcInstr64Bit.td176 [(set iPTR:$dst, ADDRri:$addr)]>;
537 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>;
538 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>;
539 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.td297 def calltarget : Operand<iPTR> {
300 def aaddr : Operand<iPTR> {
316 def memri : Operand<iPTR> {
321 def memrr : Operand<iPTR> {
325 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
330 def tocentry : Operand<iPTR> {
342 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
343 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
344 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
345 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/
DIntrinsics.gen5381 VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::i64, MVT::iPTR);
5392 VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i32, MVT::iPTR);
5397 VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::i64, MVT::iPTR);
5416 VerifyIntrinsicPrototype(ID, IF, 0, 1, MVT::iPTR);
5421 VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::i32);
5424 VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::i32, MVT::i32);
5427 VerifyIntrinsicPrototype(ID, IF, 0, 4, MVT::iPTR, MVT::i32, MVT::i32, MVT::i32);
5430 VerifyIntrinsicPrototype(ID, IF, 0, 2, MVT::iPTR, MVT::iPTR);
5433 VerifyIntrinsicPrototype(ID, IF, 0, 3, MVT::iPTR, MVT::iPTR, MVT::iPTR);
5436 VerifyIntrinsicPrototype(ID, IF, 0, 4, MVT::iPTR, MVT::iPTR, MVT::iPTR, MVT::i32);
[all …]
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.td19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
638 def calltarget : Operand<iPTR> {
784 def uimm # I # _ptr : Operand<iPTR> {
934 class mem_generic : Operand<iPTR> {
993 def mem_ea : Operand<iPTR> {
1000 def PtrRC : Operand<iPTR> {
1081 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
1084 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
1087 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
1089 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
[all …]

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