/external/vixl/src/aarch32/ |
D | disasm-aarch32.cc | 31644 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local 31648 imm6; in DecodeT32() 31674 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local 31678 imm6; in DecodeT32() 31704 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local 31708 imm6; in DecodeT32() 31734 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local 31738 imm6; in DecodeT32() 31923 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local 31927 imm6; in DecodeT32() [all …]
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D | assembler-aarch32.cc | 23291 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrn() local 23295 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrn() 23314 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrn() local 23317 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrn() 23343 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrun() local 23346 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrun() 23364 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrun() local 23367 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrun() 23427 uint32_t imm6 = imm; in vqshl() local 23431 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqshl() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrNEON.td | 3135 let Inst{21-19} = 0b001; // imm6 = 001xxx 3139 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3143 let Inst{21} = 0b1; // imm6 = 1xxxxx 3147 // imm6 = xxxxxx 3152 let Inst{21-19} = 0b001; // imm6 = 001xxx 3156 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3160 let Inst{21} = 0b1; // imm6 = 1xxxxx 3164 // imm6 = xxxxxx 3172 let Inst{21-19} = 0b001; // imm6 = 001xxx 3176 let Inst{21-20} = 0b01; // imm6 = 01xxxx [all …]
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D | ARMInstrFormats.td | 197 // other shift immediates. The imm6 field is encoded like so: 200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 203 // 64 64 - <imm> is encoded in imm6<5:0>
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-basic-a64-undefined.txt | 16 # ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrNEON.td | 3884 let Inst{21-19} = 0b001; // imm6 = 001xxx 3888 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3892 let Inst{21} = 0b1; // imm6 = 1xxxxx 3896 // imm6 = xxxxxx 3901 let Inst{21-19} = 0b001; // imm6 = 001xxx 3905 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3909 let Inst{21} = 0b1; // imm6 = 1xxxxx 3913 // imm6 = xxxxxx 3921 let Inst{21-19} = 0b001; // imm6 = 001xxx 3925 let Inst{21-20} = 0b01; // imm6 = 01xxxx [all …]
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D | ARMInstrFormats.td | 217 // other shift immediates. The imm6 field is encoded like so: 220 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 221 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 222 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 223 // 64 64 - <imm> is encoded in imm6<5:0>
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/external/valgrind/VEX/priv/ |
D | host_arm64_defs.h | 221 UInt imm6; /* 1 .. 63 */ member 230 extern ARM64RI6* ARM64RI6_I6 ( UInt imm6 );
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D | host_arm_isel.c | 3268 UInt imm6; in iselNeon64Expr_wrk() local 3274 imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; in iselNeon64Expr_wrk() 3275 vassert(imm6 <= 32 && imm6 > 0); in iselNeon64Expr_wrk() 3276 imm6 = 64 - imm6; in iselNeon64Expr_wrk() 3284 addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False)); in iselNeon64Expr_wrk() 5354 UInt imm6; in iselNeonExpr_wrk() local 5360 imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; in iselNeonExpr_wrk() 5361 vassert(imm6 <= 32 && imm6 > 0); in iselNeonExpr_wrk() 5362 imm6 = 64 - imm6; in iselNeonExpr_wrk() 5370 addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True)); in iselNeonExpr_wrk()
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D | host_arm64_defs.c | 423 ARM64RI6* ARM64RI6_I6 ( UInt imm6 ) { in ARM64RI6_I6() argument 426 ri6->ARM64ri6.I6.imm6 = imm6; in ARM64RI6_I6() 427 vassert(imm6 > 0 && imm6 < 64); in ARM64RI6_I6() 440 vex_printf("#%u", ri6->ARM64ri6.I6.imm6); in ppARM64RI6() 3420 UInt sh = argR->ARM64ri6.I6.imm6; in emit_ARM64Instr()
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D | guest_arm64_toIR.c | 2698 UInt imm6 = INSN(15,10); in dis_ARM64_data_processing_immediate() local 2704 if (!is64 && imm6 >= 32) in dis_ARM64_data_processing_immediate() 2713 if (imm6 == 0) { in dis_ARM64_data_processing_immediate() 2717 vassert(imm6 > 0 && imm6 < szBits); in dis_ARM64_data_processing_immediate() 2719 binop(mkSHL(ty), mkexpr(srcHi), mkU8(szBits-imm6)), in dis_ARM64_data_processing_immediate() 2720 binop(mkSHR(ty), mkexpr(srcLo), mkU8(imm6)))); in dis_ARM64_data_processing_immediate() 2725 nameIRegOrZR(is64,nn), nameIRegOrZR(is64,mm), imm6); in dis_ARM64_data_processing_immediate() 2818 UInt imm6 = INSN(15,10); in dis_ARM64_data_processing_register() local 2824 if ((!is64 && imm6 > 31) || sh == BITS2(1,1)) { in dis_ARM64_data_processing_register() 2829 IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, False); in dis_ARM64_data_processing_register() [all …]
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D | host_arm64_isel.c | 1246 vassert(ri->ARM64ri6.I6.imm6 < 64); in iselIntExpr_RI6() 1247 vassert(ri->ARM64ri6.I6.imm6 > 0); in iselIntExpr_RI6()
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D | guest_arm_toIR.c | 5967 UInt imm6 = (theInstr >> 16) & 0x3f; in dis_neon_data_2reg_and_shift() local 5981 tmp = (L << 6) | imm6; in dis_neon_data_2reg_and_shift() 5984 shift_imm = 64 - imm6; in dis_neon_data_2reg_and_shift() 5987 shift_imm = 64 - imm6; in dis_neon_data_2reg_and_shift() 5990 shift_imm = 32 - imm6; in dis_neon_data_2reg_and_shift() 5993 shift_imm = 16 - imm6; in dis_neon_data_2reg_and_shift()
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/external/llvm/test/MC/Disassembler/ARM/ |
D | invalid-armv7.txt | 357 # imm6=0b0xxxxx -> UNDEFINED
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/external/v8/src/arm/ |
D | assembler-arm.cc | 4460 int imm6 = 0; in EncodeNeonShiftOp() local 4463 imm6 = size_in_bits + shift; in EncodeNeonShiftOp() 4468 imm6 = 2 * size_in_bits - shift; in EncodeNeonShiftOp() 4471 return 0x1E5U * B23 | d * B22 | imm6 * B16 | vd * B12 | B6 | m * B5 | B4 | in EncodeNeonShiftOp()
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/external/llvm/lib/Target/AVR/ |
D | AVRInstrInfo.td | 183 // Addressing mode pattern reg+imm6
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrFormats.td | 574 // {5-0} - imm6 596 // {5-0} - imm6 618 // {5-0} - imm6: #0, #8, #16, or #24 627 // {5-0} - imm6: #0 or #8 655 // {5-0} - imm6: #0 or #12
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_shader.c | 4277 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6); in resq_emit() local 4280 z = LLVMBuildSDiv(builder, z, imm6, ""); in resq_emit()
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