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Searched refs:imm8 (Results 1 – 25 of 90) sorted by relevance

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/external/valgrind/none/tests/amd64/
Dinsn_pclmulqdq.def1 pclmulqdq imm8[0] xmm.uq[0x00017004200ab0cd,0xc000b802f6b31753] xmm.uq[0xa0005c0252074a9a,0x50002e0…
2 pclmulqdq imm8[1] xmm.uq[0x28001701e286710d,0xd4000b81d7f0f773] xmm.uq[0xaa0005c1c2a63aaa,0x550002e…
3 pclmulqdq imm8[16] xmm.uq[0x2a800171beae2d11,0xd54000b9b604d579] xmm.uq[0xaaa0005db1b029ad,0x955000…
4 pclmulqdq imm8[17] xmm.uq[0x8aa80018be70a8d2,0x4554000d3de61358] xmm.uq[0x22aa00077da0c89b,0xd15500…
5 pclmulqdq imm8[0] m128.uq[0x68aa8003296cd08e,0x3455400273642736] xmm.uq[0x1a2aa002185fd28a,0x0d1550…
6 pclmulqdq imm8[1] m128.uq[0x068aa801d41c9309,0xc3455401c0bc0875] xmm.uq[0xa1a2aa01c70bc327,0x90d155…
7 pclmulqdq imm8[16] m128.uq[0x4868aa81c3c78f2f,0xe4345541c8918684] xmm.uq[0x721a2aa1c2f68231,0xf90d1…
8 pclmulqdq imm8[17] m128.uq[0xbc868aa9cac23ef5,0x9e434555cc0ede67] xmm.uq[0x8f21a2abccb52e20,0x4790d…
9 pclmulqdq imm8[0] xmm.uq[0xe3c868ac4931e9ec,0x71e434570346b3e5] xmm.uq[0xf8f21a2c685118df,0xbc790d1…
10 pclmulqdq imm8[1] xmm.uq[0x5e3c868c6c18e49d,0xef1e43471cba313b] xmm.uq[0xb78f21a4650ad78e,0x5bc790d…
[all …]
Dinsn_ssse3.def49 palignr imm8[0] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988]
50 palignr imm8[1] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99]
51 palignr imm8[2] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa]
52 palignr imm8[3] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb]
53 palignr imm8[4] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc]
54 palignr imm8[5] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd]
55 palignr imm8[6] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee]
56 palignr imm8[7] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff]
57 palignr imm8[8] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134]
58 palignr imm8[9] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211]
[all …]
Dinsn_basic.def1 adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46]
2 adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47]
3 adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46]
4 adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47]
5 adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46]
6 adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47]
13 adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468]
14 adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469]
27 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
28 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
[all …]
Dinsn_sse2.def173 pextrw imm8[0] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1234]
174 pextrw imm8[1] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[5678]
175 pextrw imm8[2] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4321]
176 pextrw imm8[3] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[8765]
177 pextrw imm8[4] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1111]
178 pextrw imm8[5] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[2222]
179 pextrw imm8[6] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[3333]
180 pextrw imm8[7] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4444]
181 pinsrw imm8[0] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[65535,567…
182 pinsrw imm8[1] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[1234,6553…
[all …]
Dinsn_sse.def97 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234]
98 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678]
99 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321]
100 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765]
101 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765]
102 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765]
103 pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765]
104 pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535]
105 pinsrw imm8[0] m16.uw[0xffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765]
106 pinsrw imm8[1] m16.uw[0xffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765]
[all …]
Dinsn_mmx.def72 pslld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x12345670,0x9abcdef0]
75 psllq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x123456789abcdef0]
78 psllw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x1230,0x5670,0x9ab0,0xdef0]
81 psrad imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0xf89abcde]
84 psraw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0xf89a,0xfcde]
87 psrld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0x089abcde]
90 psrlq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x00123456789abcde]
93 psrlw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0x089a,0x0cde]
/external/valgrind/none/tests/x86/
Dinsn_ssse3.def49 palignr imm8[0] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0xffeeddccbbaa9988]
50 palignr imm8[1] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x34ffeeddccbbaa99]
51 palignr imm8[2] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x1134ffeeddccbbaa]
52 palignr imm8[3] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x221134ffeeddccbb]
53 palignr imm8[4] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x33221134ffeeddcc]
54 palignr imm8[5] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x4433221134ffeedd]
55 palignr imm8[6] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x554433221134ffee]
56 palignr imm8[7] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x66554433221134ff]
57 palignr imm8[8] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x7766554433221134]
58 palignr imm8[9] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0x77665544332211]
[all …]
Dinsn_basic.def21 adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46]
22 adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47]
23 adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46]
24 adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47]
25 adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46]
26 adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47]
33 adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468]
34 adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469]
47 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
48 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
[all …]
Dinsn_sse2.def173 pextrw imm8[0] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1234]
174 pextrw imm8[1] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[5678]
175 pextrw imm8[2] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4321]
176 pextrw imm8[3] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[8765]
177 pextrw imm8[4] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1111]
178 pextrw imm8[5] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[2222]
179 pextrw imm8[6] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[3333]
180 pextrw imm8[7] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[4444]
181 pinsrw imm8[0] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[65535,567…
182 pinsrw imm8[1] r32.ud[0xffffffff] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] => 2.uw[1234,6553…
[all …]
Dinsn_mmxext.def6 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234]
7 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678]
8 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321]
9 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765]
10 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765]
11 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765]
12 pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765]
13 pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535]
27 pshufw imm8[0x1b] mm.sw[11,22,33,44] mm.sw[0,0,0,0] => 2.sw[44,33,22,11]
28 pshufw imm8[0x1b] m64.sw[11,22,33,44] mm.sw[0,0,0,0] => 2.sw[44,33,22,11]
Dinsn_sse.def97 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234]
98 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678]
99 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321]
100 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765]
101 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765]
102 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765]
103 pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765]
104 pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535]
105 pinsrw imm8[0] m16.uw[0xffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765]
106 pinsrw imm8[1] m16.uw[0xffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765]
[all …]
Dinsn_mmx.def52 pslld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x12345670,0x9abcdef0]
55 psllq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x123456789abcdef0]
58 psllw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x1230,0x5670,0x9ab0,0xdef0]
61 psrad imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0xf89abcde]
64 psraw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0xf89a,0xfcde]
67 psrld imm8[4] mm.ud[0x01234567,0x89abcdef] => 1.ud[0x00123456,0x089abcde]
70 psrlq imm8[4] mm.uq[0x0123456789abcdef] => 1.uq[0x00123456789abcde]
73 psrlw imm8[4] mm.uw[0x0123,0x4567,0x89ab,0xcdef] => 1.uw[0x0012,0x0456,0x089a,0x0cde]
/external/elfutils/libcpu/defs/
Di3868 %mask {imm8} 8
104 00001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m}
106 00001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m}
108 00001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m}
110 00001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m}
137 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg}
138 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg}
139 01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg}
140 00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg}
142 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg}
[all …]
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/
Dsimd16intrin.h290 INLINE simdscalar _simd16_extract_ps(simd16scalar a, int imm8) in _simd16_extract_ps() argument
292 switch (imm8) in _simd16_extract_ps()
302 INLINE simdscalari _simd16_extract_si(simd16scalari a, int imm8) in _simd16_extract_si() argument
304 switch (imm8) in _simd16_extract_si()
314 INLINE simd16scalar _simd16_insert_ps(simd16scalar a, simdscalar b, int imm8) in _simd16_insert_ps() argument
316 switch (imm8) in _simd16_insert_ps()
328 INLINE simd16scalari _simd16_insert_si(simd16scalari a, simdscalari b, int imm8) in _simd16_insert_si() argument
330 switch (imm8) in _simd16_insert_si()
553 template <int imm8> in SIMD16_EMU_AVX512_2()
558 result.lo = _simd_slli_epi32(a.lo, imm8); in SIMD16_EMU_AVX512_2()
[all …]
/external/vixl/test/aarch32/config/
Dcond-rdlow-rnlow-operand-immediate-t32.json30 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, #<imm8>
35 // ADD<c>{<q>} <Rdn>, #<imm8> ; T2
36 // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
38 // ADDS{<q>} <Rdn>, #<imm8> ; T2
39 // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
43 // SUB<c>{<q>} <Rdn>, #<imm8> ; T2
44 // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
46 // SUBS{<q>} <Rdn>, #<imm8> ; T2
47 // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
136 "Adds", // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
[all …]
Dcond-rdlow-operand-imm8-t32.json28 // MNEMONIC{<c>}.N <Rdn>, #<imm8>
32 "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
33 "Mov", // MOV<c>{<q>} <Rd>, #<imm8> ; T1
34 "Movs" // MOVS{<q>} <Rd>, #<imm8> ; T1
85 "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
86 "Mov" // MOV<c>{<q>} <Rd>, #<imm8> ; T1
/external/v8/src/x64/
Dassembler-x64.h807 void instruction##p(Register dst, Immediate imm8) { \
808 shift(dst, imm8, subcode, kPointerSize); \
811 void instruction##l(Register dst, Immediate imm8) { \
812 shift(dst, imm8, subcode, kInt32Size); \
815 void instruction##q(Register dst, Immediate imm8) { \
816 shift(dst, imm8, subcode, kInt64Size); \
819 void instruction##p(Operand dst, Immediate imm8) { \
820 shift(dst, imm8, subcode, kPointerSize); \
823 void instruction##l(Operand dst, Immediate imm8) { \
824 shift(dst, imm8, subcode, kInt32Size); \
[all …]
Dassembler-x64.cc989 void Assembler::cmpb_al(Immediate imm8) { in cmpb_al() argument
990 DCHECK(is_int8(imm8.value_) || is_uint8(imm8.value_)); in cmpb_al()
993 emit(imm8.value_); in cmpb_al()
2816 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) { in extractps() argument
2818 DCHECK(is_uint8(imm8)); in extractps()
2826 emit(imm8); in extractps()
2829 void Assembler::pextrb(Register dst, XMMRegister src, int8_t imm8) { in pextrb() argument
2831 DCHECK(is_uint8(imm8)); in pextrb()
2839 emit(imm8); in pextrb()
2842 void Assembler::pextrb(const Operand& dst, XMMRegister src, int8_t imm8) { in pextrb() argument
[all …]
/external/v8/src/x87/
Dassembler-x87.cc390 void Assembler::mov_b(const Operand& dst, int8_t imm8) { in mov_b() argument
394 EMIT(imm8); in mov_b()
679 void Assembler::cmpb(const Operand& op, Immediate imm8) { in cmpb() argument
680 DCHECK(imm8.is_int8() || imm8.is_uint8()); in cmpb()
688 emit_b(imm8); in cmpb()
945 void Assembler::rcl(Register dst, uint8_t imm8) { in rcl() argument
947 DCHECK(is_uint5(imm8)); // illegal shift count in rcl()
948 if (imm8 == 1) { in rcl()
954 EMIT(imm8); in rcl()
959 void Assembler::rcr(Register dst, uint8_t imm8) { in rcr() argument
[all …]
Dassembler-x87.h604 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); } in mov_b() argument
605 void mov_b(const Operand& dst, int8_t imm8);
675 void cmpb(Register reg, Immediate imm8) { cmpb(Operand(reg), imm8); } in cmpb() argument
676 void cmpb(const Operand& op, Immediate imm8);
737 void rcl(Register dst, uint8_t imm8);
738 void rcr(Register dst, uint8_t imm8);
740 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); } in ror() argument
741 void ror(const Operand& dst, uint8_t imm8);
745 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); } in sar() argument
746 void sar(const Operand& dst, uint8_t imm8);
[all …]
Ddisasm-x87.cc563 int imm8 = -1; in D1D3C1Instruction() local
593 imm8 = 1; in D1D3C1Instruction()
595 imm8 = *(data + 1); in D1D3C1Instruction()
600 if (imm8 >= 0) { in D1D3C1Instruction()
601 AppendToBuffer(",%d", imm8); in D1D3C1Instruction()
1135 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
1139 static_cast<int>(imm8)); in InstructionDecode()
1157 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
1160 NameOfCPURegister(regop), static_cast<int>(imm8)); in InstructionDecode()
1361 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
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/external/v8/src/ia32/
Dassembler-ia32.cc808 void Assembler::cmpb(const Operand& op, Immediate imm8) { in cmpb() argument
809 DCHECK(imm8.is_int8() || imm8.is_uint8()); in cmpb()
817 emit_b(imm8); in cmpb()
1074 void Assembler::rcl(Register dst, uint8_t imm8) { in rcl() argument
1076 DCHECK(is_uint5(imm8)); // illegal shift count in rcl()
1077 if (imm8 == 1) { in rcl()
1083 EMIT(imm8); in rcl()
1088 void Assembler::rcr(Register dst, uint8_t imm8) { in rcr() argument
1090 DCHECK(is_uint5(imm8)); // illegal shift count in rcr()
1091 if (imm8 == 1) { in rcr()
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Ddisasm-ia32.cc627 int imm8 = -1; in D1D3C1Instruction() local
657 imm8 = 1; in D1D3C1Instruction()
659 imm8 = *(data + 1); in D1D3C1Instruction()
664 if (imm8 >= 0) { in D1D3C1Instruction()
665 AppendToBuffer(",%d", imm8); in D1D3C1Instruction()
1482 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
1486 static_cast<int>(imm8)); in InstructionDecode()
1504 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
1507 NameOfCPURegister(regop), static_cast<int>(imm8)); in InstructionDecode()
1708 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
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/external/valgrind/VEX/priv/
Dguest_generic_x87.c788 UInt imm8, Bool isxSTRM ) in compute_PCMPxSTRx() argument
790 vassert(imm8 < 0x80); in compute_PCMPxSTRx()
797 switch (imm8) { in compute_PCMPxSTRx()
813 UInt fmt = (imm8 >> 0) & 3; // imm8[1:0] data format in compute_PCMPxSTRx()
814 UInt agg = (imm8 >> 2) & 3; // imm8[3:2] aggregation fn in compute_PCMPxSTRx()
815 UInt pol = (imm8 >> 4) & 3; // imm8[5:4] polarity in compute_PCMPxSTRx()
816 UInt idx = (imm8 >> 6) & 1; // imm8[6] 1==msb/bytemask in compute_PCMPxSTRx()
1045 UInt imm8, Bool isxSTRM ) in compute_PCMPxSTRx_wide() argument
1047 vassert(imm8 < 0x80); in compute_PCMPxSTRx_wide()
1054 switch (imm8) { in compute_PCMPxSTRx_wide()
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/external/vixl/src/aarch32/
Dinstructions-aarch32.cc629 uint32_t imm8 = imm >> (24 - shift); in ImmediateT32() local
631 if ((imm8 <= 0xff) && ((imm8 & 0x80) != 0) && (overflow == 0)) { in ImmediateT32()
632 SetEncodingValue(((shift + 8) << 7) | (imm8 & 0x7F)); in ImmediateT32()
686 uint32_t imm8 = (imm << rot) | (imm >> (32 - rot)); in ImmediateA32() local
687 if (imm8 <= 0xff) { in ImmediateA32()
688 SetEncodingValue((rot << 7) | imm8); in ImmediateA32()

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