Home
last modified time | relevance | path

Searched refs:in1 (Results 1 – 25 of 298) sorted by relevance

12345678910>>...12

/external/valgrind/none/tests/mips64/
Dextract_insert_bit_field.stdout.exp-mips64r22 ins :: in 0x0, in1 0x0, out 0x0, pos: 0, size: 1
3 ins :: in 0x0, in1 0xffffffffffffffff, out 0xfffffffffffffffe, pos: 0, size: 1
4 ins :: in 0x0, in1 0x98765432, out 0xffffffff98765432, pos: 0, size: 1
5 ins :: in 0x0, in1 0xffffffffff865421, out 0xffffffffff865420, pos: 0, size: 1
6 ins :: in 0xffffffffffffffff, in1 0x0, out 0x1, pos: 0, size: 1
7 ins :: in 0xffffffffffffffff, in1 0xffffffffffffffff, out 0xffffffffffffffff, pos: 0, size: 1
8 ins :: in 0xffffffffffffffff, in1 0x98765432, out 0xffffffff98765433, pos: 0, size: 1
9 ins :: in 0xffffffffffffffff, in1 0xffffffffff865421, out 0xffffffffff865421, pos: 0, size: 1
10 ins :: in 0x98765432, in1 0x0, out 0x0, pos: 0, size: 1
11 ins :: in 0x98765432, in1 0xffffffffffffffff, out 0xfffffffffffffffe, pos: 0, size: 1
[all …]
/external/libvpx/libvpx/vp9/encoder/mips/msa/
Dvp9_fdct4x4_msa.c18 v8i16 in0, in1, in2, in3, in4; in vp9_fwht4x4_msa() local
20 LD_SH4(input, src_stride, in0, in1, in2, in3); in vp9_fwht4x4_msa()
22 in0 += in1; in vp9_fwht4x4_msa()
25 SUB2(in4, in1, in4, in2, in1, in2); in vp9_fwht4x4_msa()
27 in3 += in1; in vp9_fwht4x4_msa()
29 TRANSPOSE4x4_SH_SH(in0, in2, in3, in1, in0, in2, in3, in1); in vp9_fwht4x4_msa()
32 in1 -= in3; in vp9_fwht4x4_msa()
33 in4 = (in0 - in1) >> 1; in vp9_fwht4x4_msa()
36 in1 += in2; in vp9_fwht4x4_msa()
38 SLLI_4V(in0, in1, in2, in3, 2); in vp9_fwht4x4_msa()
[all …]
Dvp9_fdct8x8_msa.c18 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vp9_fht8x8_msa() local
20 LD_SH8(input, stride, in0, in1, in2, in3, in4, in5, in6, in7); in vp9_fht8x8_msa()
21 SLLI_4V(in0, in1, in2, in3, 2); in vp9_fht8x8_msa()
26 VP9_FDCT8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_fht8x8_msa()
28 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in vp9_fht8x8_msa()
30 VP9_FDCT8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_fht8x8_msa()
34 VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_fht8x8_msa()
36 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in vp9_fht8x8_msa()
38 VP9_FDCT8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_fht8x8_msa()
42 VP9_FDCT8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_fht8x8_msa()
[all …]
/external/libvpx/libvpx/vp9/common/mips/msa/
Dvp9_idct4x4_msa.c18 v8i16 in0, in1, in2, in3; in vp9_iht4x4_16_add_msa() local
21 LD4x4_SH(input, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
22 TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
27 VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
29 TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
30 VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
34 VP9_IDCT4x4(in0, in1, in2, in3, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
36 TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
37 VP9_IADST4x4(in0, in1, in2, in3, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
41 VP9_IADST4x4(in0, in1, in2, in3, in0, in1, in2, in3); in vp9_iht4x4_16_add_msa()
[all …]
Dvp9_idct8x8_msa.c18 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vp9_iht8x8_64_add_msa() local
21 LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7); in vp9_iht8x8_64_add_msa()
23 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vp9_iht8x8_64_add_msa()
29 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vp9_iht8x8_64_add_msa()
32 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in vp9_iht8x8_64_add_msa()
34 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vp9_iht8x8_64_add_msa()
39 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vp9_iht8x8_64_add_msa()
42 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in vp9_iht8x8_64_add_msa()
44 VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_iht8x8_64_add_msa()
49 VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_iht8x8_64_add_msa()
[all …]
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_sse2.c19 __m128i in0, in1; in vpx_fdct4x4_1_sse2() local
23 in1 = _mm_loadl_epi64((const __m128i *)(input + 1 * stride)); in vpx_fdct4x4_1_sse2()
24 in1 = _mm_unpacklo_epi64( in vpx_fdct4x4_1_sse2()
25 in1, _mm_loadl_epi64((const __m128i *)(input + 2 * stride))); in vpx_fdct4x4_1_sse2()
29 tmp = _mm_add_epi16(in0, in1); in vpx_fdct4x4_1_sse2()
31 in1 = _mm_unpackhi_epi16(zero, tmp); in vpx_fdct4x4_1_sse2()
33 in1 = _mm_srai_epi32(in1, 16); in vpx_fdct4x4_1_sse2()
35 tmp = _mm_add_epi32(in0, in1); in vpx_fdct4x4_1_sse2()
37 in1 = _mm_unpackhi_epi32(tmp, zero); in vpx_fdct4x4_1_sse2()
39 tmp = _mm_add_epi32(in0, in1); in vpx_fdct4x4_1_sse2()
[all …]
/external/clang/test/CodeGen/
Dmult-alt-generic.c43 register int in1 = 1; in single_lt() local
45 asm("foo %1,%0" : "=r" (out0) : "<r" (in1)); in single_lt()
47 asm("foo %1,%0" : "=r" (out0) : "r<" (in1)); in single_lt()
54 register int in1 = 1; in single_gt() local
56 asm("foo %1,%0" : "=r" (out0) : ">r" (in1)); in single_gt()
58 asm("foo %1,%0" : "=r" (out0) : "r>" (in1)); in single_gt()
65 register int in1 = 1; in single_r() local
67 asm("foo %1,%0" : "=r" (out0) : "r" (in1)); in single_r()
113 register int in1 = 1; in single_g() local
115 asm("foo %1,%0" : "=r" (out0) : "g" (in1)); in single_g()
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Dmacros_msa.h205 #define SW4(in0, in1, in2, in3, pdst, stride) \ argument
208 SW(in1, (pdst) + stride); \
220 #define SD4(in0, in1, in2, in3, pdst, stride) \ argument
223 SD(in1, (pdst) + stride); \
314 #define ST_V2(RTYPE, in0, in1, pdst, stride) \ argument
317 ST_V(RTYPE, in1, (pdst) + stride); \
323 #define ST_V4(RTYPE, in0, in1, in2, in3, pdst, stride) \ argument
325 ST_V2(RTYPE, in0, in1, (pdst), stride); \
331 #define ST_V8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) \ argument
333 ST_V4(RTYPE, in0, in1, in2, in3, pdst, stride); \
[all …]
Didct4x4_msa.c15 v8i16 in0, in1, in2, in3; in vpx_iwht4x4_16_add_msa() local
19 LD4x4_SH(input, in0, in2, in3, in1); in vpx_iwht4x4_16_add_msa()
20 TRANSPOSE4x4_SH_SH(in0, in2, in3, in1, in0, in2, in3, in1); in vpx_iwht4x4_16_add_msa()
24 UNPCK_R_SH_SW(in1, in1_r); in vpx_iwht4x4_16_add_msa()
45 PCKEV_H4_SH(in0_r, in0_r, in1_r, in1_r, in2_r, in2_r, in3_r, in3_r, in0, in1, in vpx_iwht4x4_16_add_msa()
47 ADDBLK_ST4x4_UB(in0, in3, in1, in2, dst, dst_stride); in vpx_iwht4x4_16_add_msa()
53 v8i16 in1, in0 = { 0 }; in vpx_iwht4x4_1_add_msa() local
64 in1 = in0 >> 1; in vpx_iwht4x4_1_add_msa()
65 in0 -= in1; in vpx_iwht4x4_1_add_msa()
67 ADDBLK_ST4x4_UB(in0, in1, in1, in1, dst, dst_stride); in vpx_iwht4x4_1_add_msa()
[all …]
Dfwd_txfm_msa.c15 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vpx_fdct8x8_1_msa() local
18 LD_SH8(input, stride, in0, in1, in2, in3, in4, in5, in6, in7); in vpx_fdct8x8_1_msa()
19 ADD4(in0, in1, in2, in3, in4, in5, in6, in7, in0, in2, in4, in6); in vpx_fdct8x8_1_msa()
31 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in fdct8x16_1d_column() local
44 LD_SH16(input, src_stride, in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in fdct8x16_1d_column()
46 SLLI_4V(in0, in1, in2, in3, 2); in fdct8x16_1d_column()
50 ADD4(in0, in15, in1, in14, in2, in13, in3, in12, tmp0, tmp1, tmp2, tmp3); in fdct8x16_1d_column()
55 SUB4(in0, in15, in1, in14, in2, in13, in3, in12, in15, in14, in13, in12); in fdct8x16_1d_column()
150 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in fdct16x8_1d_row() local
153 LD_SH8(input, 16, in0, in1, in2, in3, in4, in5, in6, in7); in fdct16x8_1d_row()
[all …]
Didct8x8_msa.c15 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vpx_idct8x8_64_add_msa() local
18 LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7); in vpx_idct8x8_64_add_msa()
21 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vpx_idct8x8_64_add_msa()
24 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vpx_idct8x8_64_add_msa()
27 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vpx_idct8x8_64_add_msa()
30 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vpx_idct8x8_64_add_msa()
33 SRARI_H4_SH(in0, in1, in2, in3, 5); in vpx_idct8x8_64_add_msa()
36 VP9_ADDBLK_ST8x4_UB(dst, dst_stride, in0, in1, in2, in3); in vpx_idct8x8_64_add_msa()
43 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vpx_idct8x8_12_add_msa() local
49 LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7); in vpx_idct8x8_12_add_msa()
[all …]
/external/eigen/unsupported/test/
Dcxx11_tensor_device.cu27 …Context(const Eigen::Tensor<float, 3>& in1, Eigen::Tensor<float, 3>& in2, Eigen::Tensor<float, 3>&… in CPUContext()
48 const Eigen::Tensor<float, 3>& in1() const { return in1_; } in in1() function
70 …Tensor<float, 3> >& in1, Eigen::TensorMap<Eigen::Tensor<float, 3> >& in2, Eigen::TensorMap<Eigen::… in GPUContext()
91 const Eigen::TensorMap<Eigen::Tensor<float, 3> >& in1() const { return in1_; } in in1() function
116 …context->out().device(context->device()) = context->in1() + context->in2() * 3.14f + context->in1(… in test_contextual_eval()
122 …text->out().device(context->device()) = (context->in1() + context->in2()).eval() * 3.14f + context… in test_forced_contextual_eval()
128 context->out().device(context->device()) = context->in1().constant(2.718f); in test_compound_assignment()
129 context->out().device(context->device()) += context->in1() + context->in2() * 3.14f; in test_compound_assignment()
145 …context->out().reshape(shape).slice(indices, sizes).device(context->device()) = context->in1().con… in test_contraction()
156 …context->out().slice(indices, sizes).device(context->device()) = context->in1().convolve(context->… in test_1d_convolution()
[all …]
/external/deqp/data/gles3/shaders/
Dswizzle_math_operations.test11 …input vec2 in1 = [ vec2(0.1, 0.5) | vec2(1.0, 1.25) | vec2(-0.5, -2.25) | vec2(-32.0, 64.0) | vec2…
24 out0 = in0.x + in1.x;
35 …input vec2 in1 = [ vec2(0.1, 0.5) | vec2(1.0, 1.25) | vec2(-0.5, -2.25) | vec2(-32.0, 64.0) | vec2…
48 out0 = in0.xx + in1.xx;
59 …input vec2 in1 = [ vec2(0.1, 0.5) | vec2(1.0, 1.25) | vec2(-0.5, -2.25) | vec2(-32.0, 64.0) | vec2…
72 out0 = in0.xy + in1.yx;
83 …input vec2 in1 = [ vec2(0.1, 0.5) | vec2(1.0, 1.25) | vec2(-0.5, -2.25) | vec2(-32.0, 64.0) | vec2…
96 out0 = in0.yx + in1.xy;
107 …input vec2 in1 = [ vec2(0.1, 0.5) | vec2(1.0, 1.25) | vec2(-0.5, -2.25) | vec2(-32.0, 64.0) | vec2…
120 out0 = in0.yxy + in1.xyy;
[all …]
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h238 #define SW4(in0, in1, in2, in3, pdst, stride) \ argument
241 SW(in1, (pdst) + stride); \
253 #define SD4(in0, in1, in2, in3, pdst, stride) \ argument
256 SD(in1, (pdst) + stride); \
345 #define ST_B2(RTYPE, in0, in1, pdst, stride) \ argument
348 ST_B(RTYPE, in1, (pdst) + stride); \
352 #define ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride) \ argument
354 ST_B2(RTYPE, in0, in1, (pdst), stride); \
360 #define ST_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) \ argument
362 ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride); \
[all …]
/external/webp/src/dsp/
Dmsa_macro.h168 #define SW4(in0, in1, in2, in3, pdst, stride) do { \ argument
172 SW(in1, ptmp); \
179 #define SW3(in0, in1, in2, pdst, stride) do { \ argument
183 SW(in1, ptmp); \
188 #define SW2(in0, in1, pdst, stride) do { \ argument
192 SW(in1, ptmp); \
202 #define SD4(in0, in1, in2, in3, pdst, stride) do { \ argument
206 SD(in1, ptmp); \
296 #define ST_B2(RTYPE, in0, in1, pdst, stride) do { \ argument
298 ST_B(RTYPE, in1, pdst + stride); \
[all …]
/external/libvpx/libvpx/vp8/encoder/mips/msa/
Ddct_msa.c14 #define TRANSPOSE4x4_H(in0, in1, in2, in3, out0, out1, out2, out3) \ argument
18 ILVR_H2_SH(in2, in0, in3, in1, s0_m, s1_m); \
20 ILVL_H2_SH(in2, in0, in3, in1, s0_m, s1_m); \
70 v8i16 in0, in1, in2, in3; in vp8_short_fdct4x4_msa() local
77 LD_SH4(input, pitch / 2, in0, in1, in2, in3); in vp8_short_fdct4x4_msa()
78 TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3); in vp8_short_fdct4x4_msa()
80 BUTTERFLY_4(in0, in1, in2, in3, temp0, temp1, in1, in3); in vp8_short_fdct4x4_msa()
81 SLLI_4V(temp0, temp1, in1, in3, 3); in vp8_short_fdct4x4_msa()
85 temp0 = __msa_ilvr_h(in3, in1); in vp8_short_fdct4x4_msa()
86 in1 = __msa_splati_h(coeff, 3); in vp8_short_fdct4x4_msa()
[all …]
/external/boringssl/src/crypto/fipsmodule/aes/asm/
Daesv8-armx.pl76 my ($zero,$rcon,$mask,$in0,$in1,$tmp,$key)=
177 vld1.8 {$in1},[$inp],#8
183 vtbl.8 $key,{$in1},$mask
185 vst1.32 {$in1},[$out],#8
196 veor $tmp,$tmp,$in1
198 vext.8 $in1,$zero,$in1,#12
200 veor $in1,$in1,$tmp
202 veor $in1,$in1,$key
212 vld1.8 {$in1},[$inp]
218 vtbl.8 $key,{$in1},$mask
[all …]
/external/libvpx/libvpx/vpx_dsp/ppc/
Dinv_txfm_vsx.c91 #define IDCT4(in0, in1, out0, out1) \ argument
92 t0 = vec_add(in0, in1); \
93 t1 = vec_sub(in0, in1); \
98 tmp16_0 = vec_mergel(in0, in1); \
159 #define TRANSPOSE8x8(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, \ argument
161 out0 = vec_mergeh(in0, in1); \
162 out1 = vec_mergel(in0, in1); \
170 in1 = (int16x8_t)vec_mergel((int32x4_t)out0, (int32x4_t)out2); \
179 out2 = vec_perm(in1, in5, tr8_mask0); \
180 out3 = vec_perm(in1, in5, tr8_mask1); \
[all …]
/external/tensorflow/tensorflow/core/kernels/
Daggregate_ops_cpu.h38 typename TTypes<T>::ConstFlat in1,
40 Add2EigenImpl<CPUDevice, T>::Compute(d, out, in1, in2);
46 typename TTypes<T>::ConstFlat in1,
49 Add3EigenImpl<CPUDevice, T>::Compute(d, out, in1, in2, in3);
55 typename TTypes<T>::ConstFlat in1,
59 Add4EigenImpl<CPUDevice, T>::Compute(d, out, in1, in2, in3, in4);
65 typename TTypes<T>::ConstFlat in1,
70 Add5EigenImpl<CPUDevice, T>::Compute(d, out, in1, in2, in3, in4, in5);
76 typename TTypes<T>::ConstFlat in1,
82 Add6EigenImpl<CPUDevice, T>::Compute(d, out, in1, in2, in3, in4, in5, in6);
[all …]
Daggregate_ops_gpu.cu.cc35 typename TTypes<T>::ConstFlat in1, in operator ()()
37 Add2EigenImpl<GPUDevice, T>::Compute(d, out, in1, in2); in operator ()()
44 typename TTypes<T>::ConstFlat in1, in operator ()()
47 Add3EigenImpl<GPUDevice, T>::Compute(d, out, in1, in2, in3); in operator ()()
54 typename TTypes<T>::ConstFlat in1, in operator ()()
58 Add4EigenImpl<GPUDevice, T>::Compute(d, out, in1, in2, in3, in4); in operator ()()
65 typename TTypes<T>::ConstFlat in1, in operator ()()
70 Add5EigenImpl<GPUDevice, T>::Compute(d, out, in1, in2, in3, in4, in5); in operator ()()
77 typename TTypes<T>::ConstFlat in1, in operator ()()
83 Add6EigenImpl<GPUDevice, T>::Compute(d, out, in1, in2, in3, in4, in5, in6); in operator ()()
[all …]
Daggregate_ops.h30 typename TTypes<T>::ConstFlat in1,
37 typename TTypes<T>::ConstFlat in1, in Compute()
39 out.device(d) = in1 + in2; in Compute()
46 typename TTypes<T>::ConstFlat in1,
54 typename TTypes<T>::ConstFlat in1, in Compute()
57 out.device(d) = in1 + in2 + in3; in Compute()
64 typename TTypes<T>::ConstFlat in1,
73 typename TTypes<T>::ConstFlat in1, in Compute()
77 out.device(d) = in1 + in2 + in3 + in4; in Compute()
84 typename TTypes<T>::ConstFlat in1,
[all …]
/external/toybox/toys/net/
Dnetcat.c90 int sockfd=-1, in1 = 0, in2 = 0, out1 = 1, out2 = 1; in netcat_main() local
105 if (TT.filename) in1 = out2 = xopen(TT.filename, O_RDWR); in netcat_main()
133 in1 = out2 = sockfd; in netcat_main()
135 pollinate(in1, in2, out1, out2, TT.idle, TT.quit_delay); in netcat_main()
153 in1 = out2 = accept(sockfd, (struct sockaddr *)address, &len); in netcat_main()
155 if (in1<0) perror_exit("accept"); in netcat_main()
183 close(in1); in netcat_main()
186 dup2(in1, 0); in netcat_main()
187 dup2(in1, 1); in netcat_main()
188 if (toys.optflags&FLAG_L) dup2(in1, 2); in netcat_main()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/MSP430/
Dmult-alt-generic-msp430.ll33 %in1 = alloca i16, align 2
35 store i16 1, i16* %in1, align 2
36 %tmp = load i16* %in1, align 2
39 %tmp1 = load i16* %in1, align 2
48 %in1 = alloca i16, align 2
50 store i16 1, i16* %in1, align 2
51 %tmp = load i16* %in1, align 2
54 %tmp1 = load i16* %in1, align 2
63 %in1 = alloca i16, align 2
65 store i16 1, i16* %in1, align 2
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Dmult-alt-generic-powerpc.ll33 %in1 = alloca i32, align 4
35 store i32 1, i32* %in1, align 4
36 %tmp = load i32* %in1, align 4
39 %tmp1 = load i32* %in1, align 4
48 %in1 = alloca i32, align 4
50 store i32 1, i32* %in1, align 4
51 %tmp = load i32* %in1, align 4
54 %tmp1 = load i32* %in1, align 4
63 %in1 = alloca i32, align 4
65 store i32 1, i32* %in1, align 4
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/SPARC/
Dmult-alt-generic-sparc.ll33 %in1 = alloca i32, align 4
35 store i32 1, i32* %in1, align 4
36 %tmp = load i32* %in1, align 4
39 %tmp1 = load i32* %in1, align 4
48 %in1 = alloca i32, align 4
50 store i32 1, i32* %in1, align 4
51 %tmp = load i32* %in1, align 4
54 %tmp1 = load i32* %in1, align 4
63 %in1 = alloca i32, align 4
65 store i32 1, i32* %in1, align 4
[all …]

12345678910>>...12