| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_vec4_tcs.cpp | 171 const src_reg &indirect_offset) in emit_input_urb_read() argument
180 indirect_offset); in emit_input_urb_read()
193 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in emit_input_urb_read()
206 const src_reg &indirect_offset) in emit_output_urb_read() argument
213 brw_imm_ud(dst.writemask << first_component), indirect_offset); in emit_output_urb_read()
233 const src_reg &indirect_offset) in emit_urb_write() argument
242 brw_imm_ud(writemask), indirect_offset); in emit_urb_write()
271 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
291 first_component, indirect_offset); in nir_emit_intrinsic()
294 imm_offset + 1, 0, indirect_offset); in nir_emit_intrinsic()
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| D | brw_compute.c | 40 GLintptr indirect_offset = brw->compute.num_work_groups_offset; in prepare_indirect_gpgpu_walker() local
45 indirect_offset + 0); in prepare_indirect_gpgpu_walker()
48 indirect_offset + 4); in prepare_indirect_gpgpu_walker()
51 indirect_offset + 8); in prepare_indirect_gpgpu_walker()
70 indirect_offset + 0); in prepare_indirect_gpgpu_walker()
83 indirect_offset + 4); in prepare_indirect_gpgpu_walker()
96 indirect_offset + 8); in prepare_indirect_gpgpu_walker()
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| D | brw_vec4_tcs.h | 64 const src_reg &indirect_offset);
68 const src_reg &indirect_offset);
71 unsigned base_offset, const src_reg &indirect_offset);
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| D | brw_draw.c | 225 prim->indirect_offset, 5 * sizeof(GLuint)); in brw_emit_prim()
231 prim->indirect_offset + 0); in brw_emit_prim()
234 prim->indirect_offset + 4); in brw_emit_prim()
238 prim->indirect_offset + 8); in brw_emit_prim()
242 prim->indirect_offset + 12); in brw_emit_prim()
245 prim->indirect_offset + 16); in brw_emit_prim()
249 prim->indirect_offset + 12); in brw_emit_prim()
562 prims[i].indirect_offset + (prims[i].indexed ? 12 : 8); in brw_try_draw_prims()
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| D | brw_vec4_tes.cpp | 198 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
206 if (indirect_offset.file != BAD_FILE) { in nir_emit_intrinsic()
209 input_read_header, indirect_offset); in nir_emit_intrinsic()
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| D | brw_reg.h | 263 int indirect_offset:10; /* relative addressing offset */ member
393 reg.indirect_offset = 0; in brw_reg()
1021 reg.indirect_offset = offset; in brw_vec4_indirect()
1031 reg.indirect_offset = offset; in brw_vec1_indirect()
1042 reg.indirect_offset = offset; in brw_VxH_indirect()
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| D | brw_fs_nir.cpp | 2051 fs_reg indirect_offset = get_nir_src(offset_src); in emit_gs_input_load() local
2088 const fs_reg srcs[] = { icp_handle, indirect_offset }; in emit_gs_input_load()
2126 bld.ADD(new_indirect, indirect_offset, brw_imm_ud(1u)); in emit_gs_input_load()
2127 indirect_offset = new_indirect; in emit_gs_input_load()
2342 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2405 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2422 const fs_reg srcs[] = { icp_handle, indirect_offset }; in nir_emit_tcs_intrinsic()
2463 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2483 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2488 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
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| D | brw_shader.h | 80 using brw_reg::indirect_offset;
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| D | brw_eu_emit.c | 190 dest.indirect_offset); in brw_set_dest()
196 dest.indirect_offset); in brw_set_dest()
434 brw_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.indirect_offset); in brw_set_src0()
436 brw_inst_set_src0_ia16_addr_imm(devinfo, inst, reg.indirect_offset); in brw_set_src0()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_cb_compute.c | 41 GLintptr indirect_offset) in st_dispatch_compute_common() argument
66 info.indirect_offset = indirect_offset; in st_dispatch_compute_common()
79 GLintptr indirect_offset) in st_dispatch_compute_indirect() argument
84 st_dispatch_compute_common(ctx, NULL, NULL, indirect, indirect_offset); in st_dispatch_compute_indirect()
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| D | st_draw.c | 289 GLsizeiptr indirect_offset, in st_indirect_draw_vbo() argument
333 info.indirect_offset = indirect_offset; in st_indirect_draw_vbo()
350 info.indirect_offset += stride; in st_indirect_draw_vbo()
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| /external/mesa3d/src/mesa/vbo/ |
| D | vbo_context.c | 140 GLsizeiptr indirect_offset, in vbo_draw_indirect_prims() argument
162 for (i = 0; i < draw_count; ++i, indirect_offset += stride) { in vbo_draw_indirect_prims()
165 prim[i].indirect_offset = indirect_offset; in vbo_draw_indirect_prims()
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| D | vbo.h | 63 GLsizeiptr indirect_offset; member
117 GLsizeiptr indirect_offset,
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| D | vbo_primitive_restart.c | 201 new_prim.indirect_offset); in vbo_sw_primitive_restart()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_state.h | 700 unsigned indirect_offset; /**< must be 4 byte aligned */ member
787 unsigned indirect_offset; /**< must be 4 byte aligned */ member
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| /external/mesa3d/src/amd/common/ |
| D | ac_nir_to_llvm.h | 64 uint32_t indirect_offset; member
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| /external/mesa3d/src/gallium/auxiliary/util/ |
| D | u_draw.c | 149 info_in->indirect_offset, in util_draw_indirect()
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| D | u_vbuf.c | 1178 new_info.indirect_offset, 20, in u_vbuf_draw_vbo()
1185 new_info.indirect_offset, 16, in u_vbuf_draw_vbo()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_state_draw.c | 654 assert(info->indirect_offset % 4 == 0); in si_emit_draw_packets()
669 radeon_emit(cs, info->indirect_offset); in si_emit_draw_packets()
690 radeon_emit(cs, info->indirect_offset); in si_emit_draw_packets()
936 info->indirect_offset, map_size, in si_get_draw_start_count()
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| D | si_compute.c | 605 uint64_t va = base_va + info->indirect_offset; in si_setup_tgsi_grid()
667 radeon_emit(cs, info->indirect_offset); in si_emit_dispatch_packets()
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| /external/mesa3d/src/gallium/drivers/softpipe/ |
| D | sp_compute.c | 153 info->indirect_offset, in fill_grid_size()
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_program.c | 88 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0); in indirect_uniform_load() local
113 indirect_offset = qir_ADD(c, indirect_offset, in indirect_uniform_load()
118 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0)); in indirect_uniform_load()
119 indirect_offset = qir_MIN_NOIMM(c, indirect_offset, in indirect_uniform_load()
124 indirect_offset, in indirect_uniform_load()
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| /external/mesa3d/src/gallium/drivers/trace/ |
| D | tr_dump_state.c | 816 trace_dump_member(uint, state, indirect_offset); in trace_dump_draw_info()
966 trace_dump_member(uint, state, indirect_offset); in trace_dump_grid_info()
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| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| D | nve4_compute.c | 516 uint32_t offset = res->offset + info->indirect_offset; in nve4_compute_upload_input()
636 uint32_t offset = res->offset + info->indirect_offset; in nve4_launch_grid()
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| D | nvc0_compute.c | 469 uint32_t offset = res->offset + info->indirect_offset; in nvc0_launch_grid()
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