| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 439 bool isAdd = true; in EncodeAddrModeOpValues() local
444 isAdd = false; in EncodeAddrModeOpValues()
450 isAdd = false; in EncodeAddrModeOpValues()
454 return isAdd; in EncodeAddrModeOpValues()
705 bool isAdd = true; in getAddrModeImm12OpValue() local
711 isAdd = false ; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
729 isAdd = false; in getAddrModeImm12OpValue()
734 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); in getAddrModeImm12OpValue()
738 if (isAdd) in getAddrModeImm12OpValue()
759 bool isAdd = Imm8 >= 0; in getT2Imm8s4OpValue() local
[all …]
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| D | ARMAsmBackend.cpp | 218 bool isAdd = true; in adjustFixupValue() local
221 isAdd = false; in adjustFixupValue()
224 Value |= isAdd << 23; in adjustFixupValue()
369 bool isAdd = true; in adjustFixupValue() local
372 isAdd = false; in adjustFixupValue()
377 Value |= isAdd << 23; in adjustFixupValue()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 560 bool isAdd = true; in EncodeAddrModeOpValues() local
565 isAdd = false; in EncodeAddrModeOpValues()
571 isAdd = false; in EncodeAddrModeOpValues()
575 return isAdd; in EncodeAddrModeOpValues()
879 bool isAdd = true; in getAddrModeImm12OpValue() local
888 isAdd = false ; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
903 isAdd = false; in getAddrModeImm12OpValue()
906 isAdd = false; in getAddrModeImm12OpValue()
911 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
915 if (isAdd) in getAddrModeImm12OpValue()
[all …]
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| D | ARMAsmBackend.cpp | 410 bool isAdd = true; in adjustFixupValue() local
413 isAdd = false; in adjustFixupValue()
419 Value |= isAdd << 23; in adjustFixupValue()
610 bool isAdd = true; in adjustFixupValue() local
613 isAdd = false; in adjustFixupValue()
621 return Value | (isAdd << 23); in adjustFixupValue()
630 bool isAdd = true; in adjustFixupValue() local
633 isAdd = false; in adjustFixupValue()
641 Value |= isAdd << 23; in adjustFixupValue()
657 bool isAdd = true; in adjustFixupValue() local
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| /external/apache-commons-math/src/main/java/org/apache/commons/math/fraction/ |
| D | Fraction.java | 476 private Fraction addSub(Fraction fraction, boolean isAdd) { in addSub() argument
482 return isAdd ? fraction : fraction.negate(); in addSub()
495 (isAdd ? MathUtils.addAndCheck(uvp, upv) : in addSub()
506 BigInteger t = isAdd ? uvp.add(upv) : uvp.subtract(upv); in addSub()
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| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/util/ |
| D | SyntheticAccessorFSM.java | 555 boolean isAdd = ((mathOp == ADD) && !negativeConstant) || in getIncrementType()
559 if (isAdd) { in getIncrementType()
565 if (isAdd) { in getIncrementType()
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| /external/smali/dexlib2/src/main/ragel/ |
| D | SyntheticAccessorFSM.rl | 252 boolean isAdd = ((mathOp == ADD) && !negativeConstant) ||
256 if (isAdd) {
262 if (isAdd) {
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 342 bool isAdd; member
1220 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
1378 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
1380 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
1389 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
1392 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
1399 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
1407 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
1628 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, in CreatePostIdxReg() argument
1634 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /external/valgrind/VEX/priv/ |
| D | host_arm64_defs.h | 538 Bool isAdd; member
914 extern ARM64Instr* ARM64Instr_Arith ( HReg, HReg, ARM64RIA*, Bool isAdd );
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| D | host_arm64_defs.c | 820 HReg argL, ARM64RIA* argR, Bool isAdd ) { in ARM64Instr_Arith() argument
826 i->ARM64in.Arith.isAdd = isAdd; in ARM64Instr_Arith()
1378 vex_printf("%s ", i->ARM64in.Arith.isAdd ? "add" : "sub"); in ppARM64Instr()
3304 i->ARM64in.Arith.isAdd ? X10 : X11, in emit_ARM64Instr()
3313 i->ARM64in.Arith.isAdd ? X100 : X110, in emit_ARM64Instr()
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| D | host_ppc_defs.c | 796 PPCInstr* PPCInstr_AddSubC ( Bool isAdd, Bool setC, in PPCInstr_AddSubC() argument
800 i->Pin.AddSubC.isAdd = isAdd; in PPCInstr_AddSubC()
1602 i->Pin.AddSubC.isAdd ? "add" : "sub", in ppPPCInstr()
4191 Bool isAdd = i->Pin.AddSubC.isAdd; in emit_PPCInstr() local
4197 if (isAdd) { in emit_PPCInstr()
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| D | host_ppc_defs.h | 634 Bool isAdd; /* else sub */ member
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| D | guest_amd64_toIR.c | 15352 static IRTemp math_HADDPS_128 ( IRTemp dV, IRTemp sV, Bool isAdd ) in math_HADDPS_128() argument
15368 assign( res, triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, in math_HADDPS_128()
15374 static IRTemp math_HADDPD_128 ( IRTemp dV, IRTemp sV, Bool isAdd ) in math_HADDPD_128() argument
15390 assign( res, triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, in math_HADDPD_128()
15448 Bool isAdd = opc == 0x7C; in dis_ESC_0F__SSE3() local
15449 const HChar* str = isAdd ? "add" : "sub"; in dis_ESC_0F__SSE3()
15465 putXMMReg( rG, mkexpr( math_HADDPS_128 ( gV, eV, isAdd ) ) ); in dis_ESC_0F__SSE3()
15473 Bool isAdd = opc == 0x7C; in dis_ESC_0F__SSE3() local
15474 const HChar* str = isAdd ? "add" : "sub"; in dis_ESC_0F__SSE3()
15490 putXMMReg( rG, mkexpr( math_HADDPD_128 ( gV, eV, isAdd ) ) ); in dis_ESC_0F__SSE3()
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| D | host_arm64_isel.c | 1540 Bool isAdd = e->Iex.Binop.op == Iop_Add64 in iselIntExpr_R_wrk() local
1545 addInstr(env, ARM64Instr_Arith(dst, argL, argR, isAdd)); in iselIntExpr_R_wrk()
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| D | guest_arm64_toIR.c | 2996 Bool isAdd = INSN(15,15) == 0; in dis_ARM64_data_processing_register() local
3003 binop(isAdd ? Iop_Add64 : Iop_Sub64, in dis_ARM64_data_processing_register()
3009 binop(isAdd ? Iop_Add32 : Iop_Sub32, in dis_ARM64_data_processing_register()
3014 isAdd ? "madd" : "msub", in dis_ARM64_data_processing_register()
3483 Bool isAdd = INSN(15,15) == 0; in dis_ARM64_data_processing_register() local
3497 assign(res, binop(isAdd ? Iop_Add64 : Iop_Sub64, in dis_ARM64_data_processing_register()
3500 DIP("%cm%sl %s, %s, %s, %s\n", isU ? 'u' : 's', isAdd ? "add" : "sub", in dis_ARM64_data_processing_register()
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| D | guest_x86_toIR.c | 11992 Bool isAdd = insn[2] == 0x7C; in disInstr_X86_WRK() local
11993 const HChar* str = isAdd ? "add" : "sub"; in disInstr_X86_WRK()
12020 triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, in disInstr_X86_WRK()
12037 Bool isAdd = insn[1] == 0x7C; in disInstr_X86_WRK() local
12038 const HChar* str = isAdd ? "add" : "sub"; in disInstr_X86_WRK()
12066 triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, in disInstr_X86_WRK()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 421 bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); in findInductionRegister() local
423 if (isAdd) { in findInductionRegister()
1602 bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); in fixupInductionVariable() local
1604 if (isAdd) { in fixupInductionVariable()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMCodeEmitter.cpp | 306 bool isAdd = true; in getAddrMode5OpValue() local
309 isAdd = false; in getAddrMode5OpValue()
313 if (isAdd) in getAddrMode5OpValue()
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| D | ARMInstrInfo.td | 2231 // {12} isAdd
2248 // {12} isAdd
2340 // {12} isAdd
2359 // {12} isAdd
2376 // {12} isAdd
2395 // {12} isAdd
2486 // {12} isAdd
2503 // {12} isAdd
2645 // {12} isAdd
2664 // {12} isAdd
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| D | ARMInstrFormats.td | 544 // {12} isAdd
562 // {12} isAdd
583 // {12} isAdd
636 // {8} isAdd
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 524 bool isAdd; member
2185 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
2392 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
2394 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
2403 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
2406 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
2413 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
2421 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
2822 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
2826 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 2579 // {12} isAdd
2597 // {12} isAdd
2689 // {12} isAdd
2708 // {12} isAdd
2725 // {12} isAdd
2744 // {12} isAdd
2850 // {12} isAdd
2868 // {12} isAdd
3012 // {12} isAdd
3031 // {12} isAdd
[all …]
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| D | ARMInstrFormats.td | 673 // {12} isAdd
691 // {12} isAdd
712 // {12} isAdd
765 // {8} isAdd
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX86BaseImpl.h | 5392 static bool isAdd(const Inst *Instr) {
5487 if (isAdd(BaseInst) &&
|