Searched refs:isOperationLegal (Results 1 – 13 of 13) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 718 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
724 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1472 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
1550 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { in tryFoldToZero()
2001 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2037 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2060 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { in SimplifyNodeWithTwoResults()
2070 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { in SimplifyNodeWithTwoResults()
2088 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
2099 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
[all …]
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| D | TargetLowering.cpp | 2111 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
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| D | LegalizeIntegerTypes.cpp | 359 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
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| D | SelectionDAGBuilder.cpp | 2265 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) in handleBitTestsSwitchCase()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 988 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
994 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1726 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && in visitADD()
1760 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
1847 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
2494 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2530 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2562 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { in SimplifyNodeWithTwoResults()
2578 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
2588 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
[all …]
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| D | TargetLowering.cpp | 1606 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
2853 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
2857 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : in BuildSDIV()
2931 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2934 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : in BuildUDIV()
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| D | LegalizeIntegerTypes.cpp | 426 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
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| D | SelectionDAGBuilder.cpp | 8585 if (!TLI.isOperationLegal(ISD::SHL, PTy)) in findBitTestClusters()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetLowering.h | 388 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 649 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 2009 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5663 if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT)) in EltsFromConsecutiveLoads()
14832 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { in EmitTest()
26087 TLI.isOperationLegal(Opcode, VT)) { in combineShuffle()
26376 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) { in combineExtractVectorElt()
30507 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT)) in combineUIntToFP()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 4298 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
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