| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.h | 108 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
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| D | SIISelLowering.cpp | 538 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const { in isTypeDesirableForOp() function in SITargetLowering
545 return TargetLowering::isTypeDesirableForOp(Op, VT); in isTypeDesirableForOp()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.h | 573 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
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| D | X86ISelLowering.cpp | 14265 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { in isTypeDesirableForOp() function in X86TargetLowering
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 740 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
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| D | X86InstrSSE.td | 8323 // loadi16 is tricky to fold, because !isTypeDesirableForOp, justifiably.
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| D | X86ISelLowering.cpp | 31037 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { in isTypeDesirableForOp() function in X86TargetLowering
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetLowering.h | 936 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { in isTypeDesirableForOp() function
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1479 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
1733 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
2006 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
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| D | DAGCombiner.cpp | 768 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntBinOp()
826 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntShiftOp()
870 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteExtend()
899 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteLoad()
2223 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || in SimplifyBinOpWithSameOpcodeHands()
3585 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
4888 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 701 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
1056 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
1468 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
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| D | DAGCombiner.cpp | 1038 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntBinOp()
1096 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntShiftOp()
1140 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteExtend()
1172 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteLoad()
2726 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || in SimplifyBinOpWithSameOpcodeHands()
2978 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
2979 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
4848 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
7156 TLI.isTypeDesirableForOp(ISD::SHL, VT)) { in visitTRUNCATE()
7216 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { in visitTRUNCATE()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 2389 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { in isTypeDesirableForOp() function
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