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Searched refs:lanes (Results 1 – 25 of 65) sorted by relevance

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/external/gemmlowp/meta/generators/
Dzip_Nx8_neon.py40 lanes = []
44 lanes.append(ZipLane(input_address, registers.DoubleRegister(),
48 lanes.append(ZipLane(address_register, registers.DoubleRegister(),
52 return lanes
64 def GenerateClearAggregators(emitter, lanes): argument
65 for lane in lanes:
69 def GenerateLoadAggregateStore(emitter, lanes, output_address, alignment): argument
74 for lane in lanes:
80 for lane in lanes:
88 def GenerateLeftoverLoadAggregateStore(emitter, leftovers, lanes, argument
[all …]
Dqnt_Nx8_neon.py26 def BuildName(lanes, leftovers, aligned): argument
27 name = 'qnt_%dx8' % lanes
35 def LoadAndDuplicateOffsets(emitter, registers, lanes, offsets): argument
36 if lanes == 1 or lanes == 2 or lanes == 3:
38 for unused_i in range(0, lanes):
46 raise ConfigurationError('Unsupported number of lanes: %d' % lanes)
55 lanes = []
60 lanes.append(QntLane(source,
68 lanes.append(QntLane(input_register,
77 return lanes
[all …]
Dmul_Nx8_Mx8_neon.py22 self.lanes = []
25 self.lanes.append(lane)
28 for i in range(0, len(self.lanes)):
29 registers.FreeRegister(self.lanes[i])
30 self.lanes[i] = None
34 lanes = MulLanes(address)
36 lanes.AddLane(registers.DoubleRegister())
37 return lanes
41 lanes = MulLanes(address)
42 lanes.AddLane(registers.Low(quad_register))
[all …]
Dmul_1x8_Mx8_neon.py197 def BuildName(result_type, lhs_add, rhs_add, lanes): argument
198 name = 'mul_1x8_%dx8_%s' % (lanes, result_type)
279 for lanes in range(1, 5):
280 GenerateMul1x8Mx8(emitter, result_type, lhs_add, rhs_add, lanes)
Dneon_emitter_64.py191 lanes = list(set([register.lane for register in registers]))
192 if len(lanes) > 1:
196 if lanes[0] is None:
198 elif lanes[0] is -1:
205 return '{%s}[%d]' % (', '.join(map(str, typed_registers_nolane)), lanes[0])
/external/gemmlowp/meta/
Dtest_streams_correctness.cc105 template <int lanes, int leftover>
116 prepare_row_major_data(lanes, all_elements, stride, in); in test_2()
117 Stream<std::uint8_t, lanes, 8, leftover, RowMajorWithSum>::Pack(in, params, in test_2()
119 if (check(out, lanes, all_elements)) { in test_2()
124 std::cout << "Row: " << lanes << "x8x" << leftover << " : " in test_2()
131 for (int stride = lanes; stride < lanes + 4; ++stride) { in test_2()
138 prepare_column_major_data(lanes, all_elements, stride, in); in test_2()
139 Stream<std::uint8_t, lanes, 8, leftover, ColumnMajorWithSum>::Pack(in, params, in test_2()
141 if (check(out, lanes, all_elements)) { in test_2()
146 std::cout << "Column: " << lanes << "x8x" << leftover << " : " in test_2()
[all …]
Dbase.h97 static int Scratch(const StreamType& params, int lanes);
/external/trappy/trappy/plotter/
DEventPlot.py122 lanes=None, argument
134 graph["lanes"] = self._get_lanes(lanes, lane_prefix, num_lanes, _data)
188 lanes = []
204 lanes.append({"id": idx, "label": lane})
212 lanes.append({"id": idx, "label": "{}{}".format(lane_prefix, idx)})
214 return lanes
/external/llvm/test/CodeGen/AMDGPU/
Ddetect-dead-lanes.mir1 # RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s
53 # Check defined lanes transfer; Includes checking for some special cases like
134 # Check used lanes transfer; Includes checking for some special cases like
216 # Check that copies to physregs use all lanes, copies from physregs define all
217 # lanes. So we should not get a dead/undef flag here.
315 ; let's swiffle some lanes around for fun...
327 # for the used lanes. The example reads sub3 lane at the end, however with each
371 ; rotate lanes, but skip sub2 lane...
381 # Similar to loop1 test, but check for fixpoint of defined lanes.
417 ; rotate subreg lanes, skipping sub1
/external/trappy/trappy/plotter/js/
DEventPlot.js90 itemRects, items, colourAxis, tip, lanes;
94 lanes = d.lanes;
106 mainHeight = 50 * lanes.length - margin.top - margin.bottom;
135 ext = d3.extent(lanes, function (d) {
174 .data(lanes)
192 .data(lanes)
241 lanes: lanes, property
715 var miniHeight = ePlot.lanes.length * 12 + 50;
749 .data(ePlot.lanes)
776 .data(ePlot.lanes)
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_lowering_gm107.cpp126 add->lanes = 1; /* abused for .ndv */ in handleManualTXD()
134 add->lanes = 1; /* abused for .ndv */ in handleManualTXD()
142 add->lanes = 1; /* abused for .ndv */ in handleManualTXD()
172 mov->lanes = 1 << l; in handleManualTXD()
211 insn->lanes = 0; /* abused for !.ndv */ in handleDFDX()
Dnv50_ir_emit_nv50.cpp633 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
650 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
791 code[1] |= (i->lanes << 14); in emitMOV()
2025 emitQUADOP(insn, insn->lanes, insn->subOp); in emitInstruction()
2100 if (i->join || i->lanes != 0xf || i->exit) in getMinEncodingSize()
Dnv50_ir.cpp579 lanes = 0xf; in init()
763 i->lanes = lanes; in clone()
/external/tensorflow/tensorflow/core/profiler/internal/
Dtfprof_timeline.cc349 for (int64 i = 0; i < p->lanes.size(); ++i) { in AllocateLanes()
350 const auto& lane = p->lanes[i]; in AllocateLanes()
366 l = p->lanes.size(); in AllocateLanes()
369 p->lanes.push_back(nlane); in AllocateLanes()
371 p->lanes[l][start_time] = end_time; in AllocateLanes()
Dtfprof_timeline.h69 std::vector<std::map<int64, int64>> lanes; variable
/external/tensorflow/tensorflow/python/client/
Dtimeline.py403 lanes = [0]
406 for (i, lts) in enumerate(lanes):
409 lanes[l] = ns.all_start_micros + ns.all_end_rel_micros
412 l = len(lanes)
413 lanes.append(ns.all_start_micros + ns.all_end_rel_micros)
/external/llvm/lib/Target/AArch64/
DAArch64SchedVulcan.td669 // ASIMD load, 1 element, all lanes, D-form, B/H/S
670 // ASIMD load, 1 element, all lanes, D-form, D
671 // ASIMD load, 1 element, all lanes, Q-form
691 // ASIMD load, 2 element, all lanes, D-form, B/H/S
692 // ASIMD load, 2 element, all lanes, D-form, D
693 // ASIMD load, 2 element, all lanes, Q-form
714 // ASIMD load, 3 element, all lanes, D-form, B/H/S
715 // ASIMD load, 3 element, all lanes, D-form, D
716 // ASIMD load, 3 element, all lanes, Q-form, B/H/S
717 // ASIMD load, 3 element, all lanes, Q-form, D
[all …]
DAArch64RegisterInfo.td474 class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind>
476 let Name = "TypedVectorList" # count # "_" # lanes # kind;
479 = "isTypedVectorList<" # count # ", " # lanes # ", '" # kind # "'>";
483 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string kind>
484 : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"
DAArch64Schedule.td97 // Read the unwritten lanes of the VLD's destination registers.
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-VLD3DUPd32_UPD-thumb.txt9 # A8.6.315 VLD3 (single 3-element structure to all lanes)
/external/vixl/src/aarch64/
Doperands-aarch64.h310 VRegister(unsigned code, unsigned size, unsigned lanes = 1)
311 : CPURegister(code, size, kVRegister), lanes_(lanes) { in CPURegister()
401 VIXL_DEPRECATED("GetLanes", int lanes() const) { return GetLanes(); } in lanes() function
/external/trappy/doc/
DInteractivePlotter.ipynb504 " lanes=[\"zero\", 1, \"two\", \"three\"],\n",
532 " lanes=[\"zero\", 1, \"two\", \"three\"],\n",
549 " lanes=[\"zero\", 1, \"two\", \"three\"],\n",
/external/llvm/test/CodeGen/X86/
Dvshift-4.ll16 ; shift1b can't use a packed shift but can shift lanes separately and shuffle back together
/external/clang/include/clang/Basic/
Darm_neon.td78 // - "H" - Halve the number of lanes in the type.
79 // - "D" - Double the number of lanes in the type.
94 // all lanes. The type of the vector is the base type of the intrinsic.
159 // is a width in bits to reverse. The lanes this maps to is determined
164 // mask0 - The initial sequence of lanes for shuffle ARG0
166 // mask0 - The initial sequence of lanes for shuffle ARG1
661 // E.3.16 Extract lanes from a vector
667 // E.3.17 Set lanes within a vector
679 // E.3.19 Set all lanes to same value
1115 // Set all lanes to same value
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_dc.s456 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)

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