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/external/valgrind/none/tests/mips32/
Dvfp.stdout.exp-mips32-BE2 ldc1 $f0, 0($t1) :: ft 0x666666664095a266
3 ldc1 $f0, 8($t1) :: ft 0x0bff00000
4 ldc1 $f0, 16($t1) :: ft 0x03ff00000
5 ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
8 ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
9 ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
10 ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
11 ldc1 $f0, 0($t1) :: ft 0x666666664095a266
[all …]
Dvfp.stdout.exp-mips32-LE2 ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
3 ldc1 $f0, 8($t1) :: ft 0xbff000000
4 ldc1 $f0, 16($t1) :: ft 0x3ff000000
5 ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
8 ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
9 ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
10 ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
11 ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
[all …]
Dvfp.stdout.exp-mips32r2-BE2 ldc1 $f0, 0($t1) :: ft 0x666666664095a266
3 ldc1 $f0, 8($t1) :: ft 0x0bff00000
4 ldc1 $f0, 16($t1) :: ft 0x03ff00000
5 ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
8 ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
9 ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
10 ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
11 ldc1 $f0, 0($t1) :: ft 0x666666664095a266
[all …]
Dvfp.stdout.exp-mips32r2-LE2 ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
3 ldc1 $f0, 8($t1) :: ft 0xbff000000
4 ldc1 $f0, 16($t1) :: ft 0x3ff000000
5 ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
8 ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
9 ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
10 ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
11 ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
[all …]
Dvfp.stdout.exp-mips32r2-fpu_64-LE2 ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
3 ldc1 $f0, 8($t1) :: ft 0xbff000000
4 ldc1 $f0, 16($t1) :: ft 0x3ff000000
5 ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
8 ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
9 ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
10 ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
11 ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
[all …]
Dvfp.stdout.exp-mips32r2-fpu_64-BE2 ldc1 $f0, 0($t1) :: ft 0x666666664095a266
3 ldc1 $f0, 8($t1) :: ft 0x0bff00000
4 ldc1 $f0, 16($t1) :: ft 0x03ff00000
5 ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
6 ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
7 ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
8 ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
9 ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
10 ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
11 ldc1 $f0, 0($t1) :: ft 0x666666664095a266
[all …]
/external/valgrind/none/tests/mips64/
Dfpu_load_store.stdout.exp-BE2 ldc1 :: offset: 0x0, out: 0x0
3 ldc1 :: offset: 0x8, out: 0x9823b6e0d4326d9
4 ldc1 :: offset: 0x10, out: 0x130476dc17c56b6b
5 ldc1 :: offset: 0x18, out: 0x1a864db21e475005
6 ldc1 :: offset: 0x20, out: 0x2608edb822c9f00f
7 ldc1 :: offset: 0x28, out: 0x2f8ad6d62b4bcb61
8 ldc1 :: offset: 0x30, out: 0x350c9b6431cd86d3
9 ldc1 :: offset: 0x38, out: 0x3c8ea00a384fbdbd
10 ldc1 :: offset: 0x40, out: 0x4c11db7048d0c6c7
11 ldc1 :: offset: 0x48, out: 0x4593e01e4152fda9
[all …]
Dfpu_load_store.stdout.exp-LE2 ldc1 :: offset: 0x0, out: 0x0
3 ldc1 :: offset: 0x8, out: 0xd4326d909823b6e
4 ldc1 :: offset: 0x10, out: 0x17c56b6b130476dc
5 ldc1 :: offset: 0x18, out: 0x1e4750051a864db2
6 ldc1 :: offset: 0x20, out: 0x22c9f00f2608edb8
7 ldc1 :: offset: 0x28, out: 0x2b4bcb612f8ad6d6
8 ldc1 :: offset: 0x30, out: 0x31cd86d3350c9b64
9 ldc1 :: offset: 0x38, out: 0x384fbdbd3c8ea00a
10 ldc1 :: offset: 0x40, out: 0x48d0c6c74c11db70
11 ldc1 :: offset: 0x48, out: 0x4152fda94593e01e
[all …]
/external/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-float.ll63 ; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
64 ; O32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
65 ; O32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
67 ; O32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
69 ; O32-DAG: ldc1 [[F28]], [[OFF28]]($sp)
71 ; O32-DAG: ldc1 [[F30]], [[OFF30]]($sp)
82 ; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
83 ; N32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
84 ; N32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
86 ; N32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
[all …]
Dcallee-saved-fpxx.ll52 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
53 ; O32-FPXX-DAG: ldc1 [[F22]], [[OFF22]]($sp)
54 ; O32-FPXX-DAG: ldc1 [[F24]], [[OFF24]]($sp)
55 ; O32-FPXX-DAG: ldc1 [[F26]], [[OFF26]]($sp)
56 ; O32-FPXX-DAG: ldc1 [[F28]], [[OFF28]]($sp)
57 ; O32-FPXX-DAG: ldc1 [[F30]], [[OFF30]]($sp)
Dreturn-hard-float.ll46 ; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
47 ; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
49 ; N64-DAG: ldc1 $f0, 0([[R1]])
58 ; 032FP64-DAG: ldc1 $f0, 0($sp)
59 ; 032FP64-DAG: ldc1 $f2, 8($sp)
/external/llvm/test/CodeGen/Mips/
Dselect.ll170 ; 32-DAG: ldc1 $[[F1:f0]], 16($sp)
175 ; 32R2-DAG: ldc1 $[[F1:f0]], 16($sp)
182 ; 32R6-DAG: ldc1 $[[F1:f[0-9]+]], 16($sp)
352 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
353 ; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
358 ; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
359 ; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
364 ; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
365 ; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
389 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
[all …]
Dmno-ldc1-sdc1.ll13 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
14 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
17 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
20 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
23 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
26 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
31 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
34 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
37 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
40 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
[all …]
Dmips64-f128-call.ll17 ; CHECK: ldc1 $f13, 8(${{[0-9]+}})
18 ; CHECK: ldc1 $f12, 0(${{[0-9]+}})
34 ; CHECK: ldc1 $f0, 0($[[R1]])
35 ; CHECK: ldc1 $f2, 8($[[R1]])
Dfp-indexed-ls.ll59 ; MIPS32R1: ldc1 $f0, 0($[[T3]])
66 ; MIPS32R6: ldc1 $f0, 0($[[T3]])
75 ; MIPS64R6: ldc1 $f0, 0($[[T3]])
142 ; MIPS32R1-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
146 ; MIPS32R2: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
149 ; MIPS32R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
153 ; MIPS4: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
156 ; MIPS64R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
Dfmadd1.ll191 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
197 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
203 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
232 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
238 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
244 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
273 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
279 ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
282 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
288 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
[all …]
Do32_cc.ll8 ; ALL-DAG: ldc1 $f12, %lo
9 ; ALL-DAG: ldc1 $f14, %lo
33 ; ALL-DAG: ldc1 $f14, %lo
44 ; ALL-DAG: ldc1 $f12, %lo
70 ; ALL-DAG: ldc1 $f12, %lo
84 ; ALL-DAG: ldc1 $f12, %lo
204 ; ALL-DAG: ldc1 $f12, %lo
327 ; ALL-DAG: ldc1 $f12, %lo
339 ; ALL-DAG: ldc1 $f12, %lo
Dfpxx.ll35 ; 32-FPXX: ldc1 $f0, 0($sp)
60 ; 32-FPXX: ldc1 $f0, 0($sp)
84 ; 32-FPXX: ldc1 $f0, 0($sp)
108 ; 32-FPXX: ldc1 $f0, 0($sp)
132 ; 32-FPXX: ldc1 $f0, 0($sp)
160 ; 32-FPXX: ldc1 $[[T1:f[0-9]+]], 0($sp)
163 ; 32-FPXX: ldc1 $[[T0:f[0-9]+]], 0($sp)
Dfp64a.ll44 ; 32R2-FP64A: ldc1 $f0, 0($sp)
64 ; 32R2-FP64A: ldc1 $f0, 0($sp)
84 ; 32R2-FP64A: ldc1 $f0, 0($sp)
104 ; 32R2-FP64A: ldc1 $f0, 0($sp)
131 ; 32R2-FP64A: ldc1 $[[T1:f[0-9]+]], 0($sp)
134 ; 32R2-FP64A: ldc1 $[[T0:f[0-9]+]], 0($sp)
Dfastcc.ll362 ; FP64-NOODDSPREG-DAG: ldc1 $f0, 0($[[R0]])
363 ; FP64-NOODDSPREG-DAG: ldc1 $f2, 8($[[R0]])
364 ; FP64-NOODDSPREG-DAG: ldc1 $f4, 16($[[R0]])
365 ; FP64-NOODDSPREG-DAG: ldc1 $f6, 24($[[R0]])
366 ; FP64-NOODDSPREG-DAG: ldc1 $f8, 32($[[R0]])
367 ; FP64-NOODDSPREG-DAG: ldc1 $f10, 40($[[R0]])
368 ; FP64-NOODDSPREG-DAG: ldc1 $f12, 48($[[R0]])
369 ; FP64-NOODDSPREG-DAG: ldc1 $f14, 56($[[R0]])
370 ; FP64-NOODDSPREG-DAG: ldc1 $f16, 64($[[R0]])
371 ; FP64-NOODDSPREG-DAG: ldc1 $f18, 72($[[R0]])
[all …]
/external/llvm/test/MC/Mips/
Delf-relsym.s56 ldc1 $f0, %lo($CPI0_0)($2)
58 ldc1 $f2, 0($2)
60 ldc1 $f4, %lo($CPI0_1)($3)
64 ldc1 $f0, 0($1)
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dfpcmpa.ll143 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
144 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
163 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
164 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
183 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
184 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
203 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
204 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
223 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
224 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Do32_cc.ll7 ; CHECK: ldc1 $f12, %lo
8 ; CHECK: ldc1 $f14, %lo
30 ; CHECK: ldc1 $f14, %lo
40 ; CHECK: ldc1 $f12, %lo
66 ; CHECK: ldc1 $f12, %lo
77 ; CHECK: ldc1 $f12, %lo
180 ; CHECK: ldc1 $f12, %lo
283 ; CHECK: ldc1 $f12, %lo
296 ; CHECK: ldc1 $f12, %lo
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dfp.load_store.ll49 ; MIPS32: ldc1 $f{{.*}},0{{.*}}
51 ; MIPS32O2: ldc1 $f{{.*}},0{{.*}}
117 ; MIPS32: ldc1 $f{{.*}},{{.*}}
121 ; MIPS32O2: ldc1 $f{{.*}},{{.*}}
Dfp_const_pool.ll40 ; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$8000000000000000
78 ; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$7ff8000000000000
80 ; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$7ff8000000000000
82 ; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$fff8000000000000
84 ; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$fff8000000000000

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