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Searched refs:ldrb (Results 1 – 25 of 224) sorted by relevance

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/external/boringssl/ios-arm/crypto/fipsmodule/
Daes-armv4.S190 ldrb r0,[r12,#3] @ load input data in endian-neutral
191 ldrb r4,[r12,#2] @ manner...
192 ldrb r5,[r12,#1]
193 ldrb r6,[r12,#0]
195 ldrb r1,[r12,#7]
197 ldrb r4,[r12,#6]
199 ldrb r5,[r12,#5]
200 ldrb r6,[r12,#4]
202 ldrb r2,[r12,#11]
204 ldrb r4,[r12,#10]
[all …]
/external/boringssl/linux-arm/crypto/fipsmodule/
Daes-armv4.S189 ldrb r0,[r12,#3] @ load input data in endian-neutral
190 ldrb r4,[r12,#2] @ manner...
191 ldrb r5,[r12,#1]
192 ldrb r6,[r12,#0]
194 ldrb r1,[r12,#7]
196 ldrb r4,[r12,#6]
198 ldrb r5,[r12,#5]
199 ldrb r6,[r12,#4]
201 ldrb r2,[r12,#11]
203 ldrb r4,[r12,#10]
[all …]
/external/llvm/test/CodeGen/ARM/
Dstruct_byval_arm_t1_t2.ll54 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
56 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
58 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
60 ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
63 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
140 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
143 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
163 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
165 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
167 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
[all …]
Dunaligned_load_store.ll16 ; EXPANDED: ldrb [[R2:r[0-9]+]]
17 ; EXPANDED: ldrb [[R3:r[0-9]+]]
18 ; EXPANDED: ldrb [[R12:r[0-9]+]]
19 ; EXPANDED: ldrb [[R1:r[0-9]+]]
56 ; EXPANDED: ldrb
71 ; EXPANDED: ldrb
75 ; UNALIGNED-NOT: ldrb
Dfast-isel-align.ll99 ; ARM-STRICT-ALIGN: ldrb
100 ; ARM-STRICT-ALIGN: ldrb
103 ; THUMB-STRICT-ALIGN: ldrb
104 ; THUMB-STRICT-ALIGN: ldrb
131 ; ARM-STRICT-ALIGN: ldrb
132 ; ARM-STRICT-ALIGN: ldrb
133 ; ARM-STRICT-ALIGN: ldrb
134 ; ARM-STRICT-ALIGN: ldrb
137 ; THUMB-STRICT-ALIGN: ldrb
138 ; THUMB-STRICT-ALIGN: ldrb
[all …]
Dfast-isel-intrinsic.ll232 ; ARM: ldrb r1, [r0, #16]
234 ; ARM: ldrb r1, [r0, #17]
236 ; ARM: ldrb r1, [r0, #18]
238 ; ARM: ldrb r1, [r0, #19]
240 ; ARM: ldrb r1, [r0, #20]
242 ; ARM: ldrb r1, [r0, #21]
244 ; ARM: ldrb r1, [r0, #22]
246 ; ARM: ldrb r1, [r0, #23]
248 ; ARM: ldrb r1, [r0, #24]
250 ; ARM: ldrb r1, [r0, #25]
[all …]
D2013-05-07-ByteLoadSameAddress.ll21 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
22 ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1]
37 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
38 ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1]
51 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1]
52 ; CHECK-NEXT: ldrb{{[.w]*}} r{{[0-9]*}}, [r{{[0-9]*}}, #1]
/external/libavc/common/armv8/
Dih264_padding_neon_av8.s185 ldrb w8, [x0]
187 ldrb w9, [x0]
190 ldrb w10, [x0]
195 ldrb w11, [x0]
200 ldrb w8, [x0]
203 ldrb w9, [x0]
206 ldrb w10, [x0]
210 ldrb w11, [x0]
222 ldrb w8, [x0]
224 ldrb w9, [x0]
[all …]
Dih264_intra_pred_luma_16x16_av8.s449 ldrb w8, [x7], #-1
450 ldrb w9, [x0], #1
453 ldrb w8, [x7], #-1
455 ldrb w9, [x0], #1
460 ldrb w8, [x7], #-1
461 ldrb w9, [x0], #1
464 ldrb w5, [x7], #-1
468 ldrb w9, [x0], #1
473 ldrb w8, [x7], #-1
474 ldrb w9, [x0], #1
[all …]
Dih264_intra_pred_luma_4x4_av8.s273 ldrb w5, [x10], #-1
274 ldrb w6, [x10], #-1
275 ldrb w7, [x10], #-1
277 ldrb w8, [x10], #-1
284 ldrb w6, [x10], #1
285 ldrb w7, [x10], #1
287 ldrb w8, [x10], #1
289 ldrb w9, [x10], #1
306 ldrb w6, [x10], #1
307 ldrb w7, [x10], #1
[all …]
/external/capstone/suite/MC/ARM/
Darm-memory-instructions.s.cs17 0x00,0x30,0xd8,0xe5 = ldrb r3, [r8]
18 0x3f,0x10,0xdd,0xe5 = ldrb r1, [sp, #63]
19 0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #4095]!
20 0x16,0x80,0xd1,0xe4 = ldrb r8, [r1], #22
21 0x13,0x20,0x57,0xe4 = ldrb r2, [r7], #-19
22 0x05,0x90,0xd8,0xe7 = ldrb r9, [r8, r5]
23 0x01,0x10,0x55,0xe7 = ldrb r1, [r5, -r1]
24 0x02,0x30,0xf5,0xe7 = ldrb r3, [r5, r2]!
25 0x03,0x60,0x79,0xe7 = ldrb r6, [r9, -r3]!
26 0x04,0x20,0xd1,0xe6 = ldrb r2, [r1], r4
[all …]
/external/libavc/common/arm/
Dih264_padding_neon.s176 ldrb r8, [r0], r1
177 ldrb r9, [r0], r1
179 ldrb r10, [r0], r1
183 ldrb r11, [r0], r1
187 ldrb r8, [r0], r1
189 ldrb r9, [r0], r1
191 ldrb r10, [r0], r1
194 ldrb r11, [r0], r1
205 ldrb r8, [r0], r1
206 ldrb r9, [r0], r1
[all …]
Dih264_intra_pred_luma_16x16_a9q.s420 ldrb r8, [r7], r4
421 ldrb r9, [r0], lr
426 ldrb r8, [r7], r4
429 ldrb r9, [r0], lr
435 ldrb r8, [r7], r4
436 ldrb r9, [r0], lr
439 ldrb r5, [r7], r4
444 ldrb r9, [r0], lr
450 ldrb r8, [r7], r4
451 ldrb r9, [r0], lr
[all …]
Dih264_intra_pred_luma_4x4_a9q.s186 ldrb r5, [r0], r2
188 ldrb r6, [r0], r2
191 ldrb r7, [r0], r2
194 ldrb r8, [r0], r2
272 ldrb r5, [r10], r2
273 ldrb r6, [r10], r2
274 ldrb r7, [r10], r2
276 ldrb r8, [r10], r2
283 ldrb r6, [r10], #1
284 ldrb r7, [r10], #1
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-ldrb.ll6 ; CHECK: ldrb r0, [r0]
14 ; CHECK: ldrb r0, [r0, #-1]
24 ; CHECK: ldrb r0, [r0, r1]
34 ; CHECK: ldrb r0, [r0, #-128]
44 ; CHECK: ldrb r0, [r0, r1]
54 ; CHECK: ldrb.w r0, [r0, r1, lsl #2]
66 ; CHECK: ldrb r0, [r0, r1]
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-ldrb.ll6 ; CHECK: ldrb r0, [r0]
14 ; CHECK: ldrb r0, [r0, #-1]
24 ; CHECK: ldrb r0, [r0, r1]
34 ; CHECK: ldrb r0, [r0, #-128]
44 ; CHECK: ldrb r0, [r0, r1]
54 ; CHECK: ldrb.w r0, [r0, r1, lsl #2]
66 ; CHECK: ldrb r0, [r0, r1]
/external/libhevc/common/arm/
Dihevc_deblk_luma_vert.s120 ldrb r8,[r0,#-3] @ -3 value
122 ldrb r10,[r0,#-2] @-2 value
124 ldrb r11,[r0,#-1] @-1 value
126 ldrb r12,[r0,#0] @ 0 value
127 ldrb r9,[r0,#1] @ 1 value
129 ldrb r2,[r0,#2] @ 2 value
148 ldrb r2,[r14,#-3] @ -2 value
150 ldrb r10,[r14,#-2] @ -2 value
152 ldrb r11,[r14,#-1] @ -1 value
154 ldrb r12,[r14,#0] @ 0 value
[all …]
/external/libhevc/common/arm64/
Dihevc_deblk_luma_vert.s115 ldrb w8,[x19] // -3 value
117 ldrb w10,[x19,#1] //-2 value
119 ldrb w11,[x19,#2] //-1 value
121 ldrb w12,[x0,#0] // 0 value
122 ldrb w9,[x0,#1] // 1 value
125 ldrb w2,[x0,#2] // 2 value
150 ldrb w2,[x19] // -2 value
152 ldrb w10,[x19,#1] // -2 value
154 ldrb w11,[x19,#2] // -1 value
156 ldrb w12,[x14,#0] // 0 value
[all …]
Dihevc_padding.s101 ldrb w8,[x0]
103 ldrb w9,[x0]
105 ldrb w10,[x0]
107 ldrb w11,[x0]
347 ldrb w8,[x0, #-1]
349 ldrb w9,[x0, #-1]
351 ldrb w10,[x0, #-1]
353 ldrb w11,[x0, #-1]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dunaligned_load_store.ll11 ; GENERIC: ldrb [[R2:r[0-9]+]]
12 ; GENERIC: ldrb [[R3:r[0-9]+]]
13 ; GENERIC: ldrb [[R12:r[0-9]+]]
14 ; GENERIC: ldrb [[R1:r[0-9]+]]
/external/llvm/test/CodeGen/AArch64/
Darm64-fast-isel-intrinsic.ll58 ; ARM64: ldrb w11, [x9, #16]
75 ; ARM64: ldrb w11, [x9, #16]
92 ; ARM64: ldrb w10, [x9, #8]
111 ; ARM64: ldrb w10, [x9, #6]
124 ; ARM64: ldrb w10, [x9]
126 ; ARM64: ldrb w10, [x9, #1]
128 ; ARM64: ldrb w10, [x9, #2]
130 ; ARM64: ldrb w10, [x9, #3]
142 ; ARM64: ldrb [[BYTE:w[0-9]+]], [x[[ADDR]]]
Dbool-loads.ll10 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
22 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
37 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
51 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
Darm64-addr-type-promotion.ll15 ; CHECK-NEXT: ldrb [[BLOCKVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE]], w0, sxtw]
16 ; CHECK-NEXT: ldrb [[BLOCKVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE]], w1, sxtw]
22 ; CHECK-NEXT: ldrb [[LOADEDVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE1]], #1]
23 ; CHECK-NEXT: ldrb [[LOADEDVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE2]], #1]
27 ; CHECK: ldrb [[LOADEDVAL3:w[0-9]+]], {{\[}}[[BLOCKBASE1]], #2]
28 ; CHECK-NEXT: ldrb [[LOADEDVAL4:w[0-9]+]], {{\[}}[[BLOCKBASE2]], #2]
/external/llvm/test/CodeGen/Thumb/
Dldr_ext.ll7 ; V5: ldrb
9 ; V6: ldrb
25 ; V5: ldrb
29 ; V6: ldrb
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/
Dldr_ext.ll7 ; V5: ldrb
9 ; V6: ldrb
25 ; V5: ldrb
29 ; V6: ldrb

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