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Searched refs:ldrd (Results 1 – 25 of 67) sorted by relevance

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/external/llvm/test/MC/ARM/
Darm-ldrd.s5 ldrd r1, r2, [pc, #0] label
6 ldrd r1, r2, [r3, #4] label
7 ldrd r1, r2, [r3], #4 label
8 ldrd r1, r2, [r3, #4]! label
9 ldrd r1, r2, [r3, -r4]! label
10 ldrd r1, r2, [r3, r4] label
11 ldrd r1, r2, [r3], r4 label
20 ldrd r0, r3, [pc, #0] label
21 ldrd r0, r3, [r4, #4] label
22 ldrd r0, r3, [r4], #4 label
[all …]
Dldrd-strd-gnu-thumb.s8 @ CHECK: ldrd r0, r1, [r10, #512]! @ encoding: [0xfa,0xe9,0x80,0x01]
9 @ CHECK: ldrd r0, r1, [r10], #512 @ encoding: [0xfa,0xe8,0x80,0x01]
10 @ CHECK: ldrd r0, r1, [r10, #512] @ encoding: [0xda,0xe9,0x80,0x01]
11 ldrd r0, [r10, #512]!
12 ldrd r0, [r10], #512
13 ldrd r0, [r10, #512]
Dldrd-strd-gnu-arm.s8 @ CHECK: ldrd r0, r1, [r10, #32]! @ encoding: [0xd0,0x02,0xea,0xe1]
9 @ CHECK: ldrd r0, r1, [r10], #32 @ encoding: [0xd0,0x02,0xca,0xe0]
10 @ CHECK: ldrd r0, r1, [r10, #32] @ encoding: [0xd0,0x02,0xca,0xe1]
11 ldrd r0, [r10, #32]!
12 ldrd r0, [r10], #32
13 ldrd r0, [r10, #32]
Dthumb2-ldrd.s6 ldrd r0, r0, [pc, #0] label
7 ldrd r0, r0, [r1, #4] label
8 ldrd r0, r0, [r1], #4 label
9 ldrd r0, r0, [r1, #4]! label
Dldrd-strd-gnu-arm-bad-imm.s4 @ CHECK: ldrd r0, [r0, #512]
5 ldrd r0, [r0, #512]
Dldrd-strd-gnu-thumb-bad-regs.s5 @ CHECK: ldrd r12, [r0, #512]
6 ldrd r12, [r0, #512]
Dldrd-strd-gnu-sp.s6 ldrd r12, [r0, #32]
Dinvalid-vector-index.s3 ldrd r6, r7 [r2, #15] label
/external/llvm/test/CodeGen/ARM/
Dldrd.ll21 ; A8: ldrd r0, r1, [r0]
24 ; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]]
25 ; CONSERVATIVE-NOT: ldrd
47 ; BASIC: ldrd
50 ; GREEDY: ldrd
86 ; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4]
89 ; CONSERVATIVE-NOT: ldrd
103 ; CONSERVATIVE-NOT: ldrd
104 ; A8: ldrd
126 ; A8: ldrd r2, r1, [sp]
[all …]
D2011-03-15-LdStMultipleBug.ll3 ; Do not form Thumb2 ldrd / strd if the offset is not multiple of 4.
13 ; CHECK-NOT: ldrd
D2012-10-04-AAPCS-byval-align8.ll32 ; CHECK: ldrd r2, [[TMP:r[0-9]+]], {{\[}}[[BASE]]{{\]}}
59 ; CHECK: ldrd r2, [[TMP:r[0-9]+]], {{\[}}[[BASE]]{{\]}}
Dgpr-paired-spill.ll22 ; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
23 ; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
Dinlineasm-64bit.ll59 %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
65 ; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
66 %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
/external/capstone/suite/MC/ARM/
Darm-memory-instructions.s.cs34 0xd0,0x20,0xc5,0xe1 = ldrd r2, r3, [r5]
35 0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #15]
36 0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #32]!
37 0xd8,0x60,0xc1,0xe0 = ldrd r6, r7, [r1], #8
38 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
39 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
40 0xd0,0x00,0x48,0xe0 = ldrd r0, r1, [r8], #-0
41 0xd3,0x40,0x81,0xe1 = ldrd r4, r5, [r1, r3]
42 0xd2,0x40,0xa7,0xe1 = ldrd r4, r5, [r7, r2]!
43 0xdc,0x00,0x88,0xe0 = ldrd r0, r1, [r8], r12
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dmemory-arm-instructions.txt107 # CHECK: ldrd r0, r1, [r5]
108 # CHECK: ldrd r8, r9, [r2, #15]
109 # CHECK: ldrd r2, r3, [r9, #32]!
110 # CHECK: ldrd r6, r7, [r1], #8
111 # CHECK: ldrd r2, r3, [r8], #0
112 # CHECK: ldrd r2, r3, [r8], #0
113 # CHECK: ldrd r2, r3, [r8], #-0
131 # CHECK: ldrd r4, r5, [r1, r3]
132 # CHECK: ldrd r4, r5, [r7, r2]!
133 # CHECK: ldrd r0, r1, [r8], r12
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dmemory-arm-instructions.txt107 # CHECK: ldrd r0, r1, [r5]
108 # CHECK: ldrd r8, r9, [r2, #15]
109 # CHECK: ldrd r2, r3, [r9, #32]!
110 # CHECK: ldrd r6, r7, [r1], #8
111 # CHECK: ldrd r2, r3, [r8], #0
112 # CHECK: ldrd r2, r3, [r8], #0
113 # CHECK: ldrd r2, r3, [r8], #-0
131 # CHECK: ldrd r4, r5, [r1, r3]
132 # CHECK: ldrd r4, r5, [r7, r2]!
133 # CHECK: ldrd r0, r1, [r8], r12
[all …]
Dldrd-armv4.txt13 # V5TE: ldrd
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-ldm.ll9 ; CHECK: ldrd
10 ; CONSERVATIVE-NOT: ldrd
23 ; CONSERVATIVE-NOT: ldrd
37 ; CONSERVATIVE-NOT: ldrd
Daapcs.ll36 ; SOFT: ldrd r0, r1, [sp, #48]
44 ; SOFT: ldrd r0, r1, [sp, #48]
Dthumb2-ldrd.ll7 ; CHECK: ldrd
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Ddiagnostics.s287 @ Out of order Rt/Rt2 operands for ldrd
288 ldrd r4, r3, [r8]
289 ldrd r4, r3, [r8, #8]!
290 ldrd r4, r3, [r8], #8
292 @ CHECK-ERRORS: ldrd r4, r3, [r8]
295 @ CHECK-ERRORS: ldrd r4, r3, [r8, #8]!
298 @ CHECK-ERRORS: ldrd r4, r3, [r8], #8
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
D2011-03-15-LdStMultipleBug.ll3 ; Do not form Thumb2 ldrd / strd if the offset is not multiple of 4.
13 ; CHECK-NOT: ldrd
Dmemcpy-inline.ll4 ; CHECK: ldrd
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-ldrd.ll7 ;CHECK: ldrd r2, r3, [r2]
/external/vixl/doc/aarch32/design/
Dliteral-pool-aarch32.md15 For example, ldrd's range is [-1020, 1020] for 32bit T32 and [-255, 255] for
58 range (ldrd for example), that this will be hard to avoid.
70 ranges like ldrd and one other for bigger ranges.

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