| /external/capstone/suite/MC/AArch64/ |
| D | neon-mov.s.cs | 4 0x2f,0x24,0x00,0x0f = movi v15.2s, #0x1, lsl #8
5 0x30,0x44,0x00,0x0f = movi v16.2s, #0x1, lsl #16
6 0x3f,0x64,0x00,0x0f = movi v31.2s, #0x1, lsl #24
8 0x20,0x24,0x00,0x4f = movi v0.4s, #0x1, lsl #8
9 0x20,0x44,0x00,0x4f = movi v0.4s, #0x1, lsl #16
10 0x20,0x64,0x00,0x4f = movi v0.4s, #0x1, lsl #24
12 0x20,0xa4,0x00,0x0f = movi v0.4h, #0x1, lsl #8
14 0x20,0xa4,0x00,0x4f = movi v0.8h, #0x1, lsl #8
17 0x20,0x24,0x00,0x2f = mvni v0.2s, #0x1, lsl #8
18 0x20,0x44,0x00,0x2f = mvni v0.2s, #0x1, lsl #16
[all …]
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| /external/llvm/test/MC/AArch64/ |
| D | neon-mov.s | 11 movi v15.2s, #1, lsl #8
12 movi v16.2s, #1, lsl #16
13 movi v31.2s, #1, lsl #24
15 movi v0.4s, #1, lsl #8
16 movi v0.4s, #1, lsl #16
17 movi v0.4s, #1, lsl #24
19 movi v0.4h, #1, lsl #8
21 movi v0.8h, #1, lsl #8
42 mvni v0.2s, #1, lsl #8
43 mvni v0.2s, #1, lsl #16
[all …]
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| D | alias-addsubimm.s | 5 sub w0, w2, #2, lsl 12
6 add w0, w2, #-2, lsl 12
9 sub x1, x3, #2, lsl 12
10 add x1, x3, #-2, lsl 12
17 sub x1, x3, #4095, lsl 0
18 add x1, x3, #-4095, lsl 0
24 add w0, w2, #2, lsl 12
25 sub w0, w2, #-2, lsl 12
28 add x1, x3, #2, lsl 12
29 sub x1, x3, #-2, lsl 12
[all …]
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| D | arm64-aliases.s | 43 ands wzr, w1, w2, lsl #2
44 ands xzr, x1, x2, lsl #3
45 tst w3, w7, lsl #31
52 ; CHECK: tst w1, w2, lsl #2 ; encoding: [0x3f,0x08,0x02,0x6a]
53 ; CHECK: tst x1, x2, lsl #3 ; encoding: [0x3f,0x0c,0x02,0xea]
54 ; CHECK: tst w3, w7, lsl #31 ; encoding: [0x7f,0x7c,0x07,0x6a]
60 cmn w1, #3, lsl #0
70 ; CHECK: cmn x2, #0x400, lsl #12 ; encoding: [0x5f,0x00,0x50,0xb1]
82 cmp w1, #1024, lsl #12
93 cmp wsp, w9, lsl #0
[all …]
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| D | arm64-arithmetic-encoding.s | 33 add w3, w4, #1024, lsl #0
35 add x3, x4, #1024, lsl #0
42 add w3, w4, #1024, lsl #12
44 add w3, w4, #0, lsl #12
45 add x3, x4, #1024, lsl #12
47 add x3, x4, #0, lsl #12
50 ; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11]
51 ; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11]
52 ; CHECK: add w3, w4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x11]
53 ; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91]
[all …]
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| D | arm64-logical-encoding.s | 52 and w1, w2, w3, lsl #2
53 and x1, x2, x3, lsl #2
63 ; CHECK: and w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x0a]
64 ; CHECK: and x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0x8a]
74 ands w1, w2, w3, lsl #2
75 ands x1, x2, x3, lsl #2
85 ; CHECK: ands w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x6a]
86 ; CHECK: ands x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0xea]
96 bic w1, w2, w3, lsl #3
97 bic x1, x2, x3, lsl #3
[all …]
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| D | basic-a64-diagnostics.s | 69 add sp, x5, x7, lsl
81 add w4, w5, #-4096, lsl #12
82 add w5, w6, #0x1000, lsl #12
97 add w2, w3, #0x1, lsl #1
98 add w5, w17, #0xfff, lsl #13
99 add w17, w20, #0x1000, lsl #12
100 sub xsp, x34, #0x100, lsl #-1
152 subs x5, xzr, #0x456, lsl #12
165 mov wsp, w27, #0xfff, lsl #12
197 add w1, w2, w3, lsl #-1
[all …]
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| /external/valgrind/none/tests/arm/ |
| D | v6intThumb.stdout.exp | 2145 adds.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2146 adds.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2147 adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2148 adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000…
2157 add.w r1, r2, r3, lsl #0 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2158 add.w r1, r2, r3, lsl #1 :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2159 add.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2160 add.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000…
2169 adds.w r1, r2, r3, lsl #0 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000…
2170 adds.w r1, r2, r3, lsl #1 :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000…
[all …]
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| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | aes-armv4.S | 194 orr r0,r0,r4,lsl#8
196 orr r0,r0,r5,lsl#16
198 orr r0,r0,r6,lsl#24
201 orr r1,r1,r4,lsl#8
203 orr r1,r1,r5,lsl#16
205 orr r1,r1,r6,lsl#24
208 orr r2,r2,r4,lsl#8
210 orr r2,r2,r5,lsl#16
212 orr r2,r2,r6,lsl#24
215 orr r3,r3,r4,lsl#8
[all …]
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| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | aes-armv4.S | 193 orr r0,r0,r4,lsl#8
195 orr r0,r0,r5,lsl#16
197 orr r0,r0,r6,lsl#24
200 orr r1,r1,r4,lsl#8
202 orr r1,r1,r5,lsl#16
204 orr r1,r1,r6,lsl#24
207 orr r2,r2,r4,lsl#8
209 orr r2,r2,r5,lsl#16
211 orr r2,r2,r6,lsl#24
214 orr r3,r3,r4,lsl#8
[all …]
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_tns_ar_filter_fixed_32x16.s | 66 MOV r8, r8, lsl r1
68 MOV r8 , r8 , lsl r6
76 MOV r5 , r5 , lsl #1
78 ADD r14, r12, r5, lsl #1
86 MOV r8, r8, lsl r1
87 SUB r8 , r8 , r11, lsl #1
91 MOV r8 , r8 , lsl r6
110 MOV r5 , r4 , lsl #1
113 ADD r14 , r12, r5, lsl #1
135 MOV r8, r8, lsl r1
[all …]
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| D | ixheaacd_radix4_bfly.s | 39 MOV r3, r3, lsl #1
45 ADD r2, r1, r3, lsl #2
55 LDR r8, [r2, r3, lsl #2]
56 LDR r9, [r2, r3, lsl #3]
69 LDR r9, [r2, r3, lsl #2]!
70 LDR r10, [r2, r3, lsl #2]!
92 MOV r8, r8, lsl #1
98 MOV r8, r8, lsl #1
99 STR r8, [r2], -r3, lsl #2
105 MOV r5, r8, lsl #1
[all …]
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| D | ixheaacd_esbr_radix4bfly.s | 37 MOV r3, r3, lsl #1
43 ADD r2, r1, r3, lsl #2
53 LDR r8, [r2, r3, lsl #2]
54 LDR r9, [r2, r3, lsl #3]
67 LDR r9, [r2, r3, lsl #2]!
68 LDR r10, [r2, r3, lsl #2]!
91 MOV r8, r8, lsl #1
98 MOV r8, r8, lsl #1
99 STR r8, [r2], -r3, lsl #2
106 MOV r5, r8, lsl #1
[all …]
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| D | ixheaacd_decorr_filter2.s | 275 MOV r8, r8, lsl #1
287 MOV r3, r3, lsl #1
288 MOV r9, r9, lsl #1
484 MOV r8, r8, lsl #1
494 MOV r3, r3, lsl #1
495 MOV r9, r9, lsl #1
610 LDR r8, [r6, r7, lsl #2]
612 LDR r9, [r10, r7, lsl #2]
617 LDR r8, [r6, r7, lsl #2]
619 LDR r9, [r10, r7, lsl #2]
[all …]
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| D | ixheaacd_tns_ar_filter_fixed.s | 63 MOV r8, r8, lsl r1
65 MOV r8 , r8 , lsl r6
72 MOV r5 , r5 , lsl #2
85 MOV r8, r8, lsl r1
86 SUB r8 , r8 , r11, lsl #1
90 MOV r8 , r8 , lsl r6
146 MOV r8, r8, lsl r1 @y = (*spectrum) << scaleSpec
156 SUB r8 , r8 , r11, lsl #1 @y=sub32(y,(acc<<1))
157 MOV r2 , r8 , lsl r6 @ shl32(y, shift_value)
185 MOV r8, r8, lsl r1 @y = (*spectrum) << scaleSpec
[all …]
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| D | ixheaacd_mps_complex_fft_64_asm.s | 43 SUB r6, r4, r6, lsl#1 @x2r = x0r - (x2r << 1)@
44 SUB r7, r5, r7, lsl#1 @x2i = x0i - (x2i << 1)@
47 SUB r1, r8, r10, lsl#1 @x3r = x1r - (x3r << 1)@
48 SUB r11, r9, r11, lsl#1 @x3i = x1i - (x3i << 1)@
52 SUB r8, r4, r8, lsl#1 @x1r = x0r - (x1r << 1)@
53 SUB r9, r5, r9, lsl#1 @x1i = x0i - (x1i << 1)
56 SUB r10, r6, r11, lsl#1 @x3i = x2r - (x3i << 1)@
57 ADD r11, r7, r1, lsl#1 @x3r = x2i + (x3r << 1)@
101 SUB r8, r4, r8, lsl #1 @x2r = x0r - (x2r << 1)@
102 SUB r9, r5, r9, lsl #1 @x2i = x0i - (x2i << 1)@
[all …]
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| D | ixheaacd_complex_fft_p2.s | 55 SUB r6, r4, r6, lsl#1 @x2r = x0r - (x2r << 1)@
56 SUB r7, r5, r7, lsl#1 @x2i = x0i - (x2i << 1)@
59 SUB r1, r8, r10, lsl#1 @x3r = x1r - (x3r << 1)@
60 SUB r11, r9, r11, lsl#1 @x3i = x1i - (x3i << 1)@
64 SUB r8, r4, r8, lsl#1 @x1r = x0r - (x1r << 1)@
65 SUB r9, r5, r9, lsl#1 @x1i = x0i - (x1i << 1)
68 SUB r10, r6, r11, lsl#1 @x3i = x2r - (x3i << 1)@
69 ADD r11, r7, r1, lsl#1 @x3r = x2i + (x3r << 1)@
113 SUB r8, r4, r8, lsl #1 @x2r = x0r - (x2r << 1)@
114 SUB r9, r5, r9, lsl #1 @x2i = x0i - (x2i << 1)@
[all …]
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| D | ixheaacd_complex_ifft_p2.s | 55 SUB r6, r4, r6, lsl#1 @x2r = x0r - (x2r << 1)@
56 SUB r7, r5, r7, lsl#1 @x2i = x0i - (x2i << 1)@
59 SUB r1, r8, r10, lsl#1 @x3r = x1r - (x3r << 1)@
60 SUB r11, r9, r11, lsl#1 @x3i = x1i - (x3i << 1)@
64 SUB r8, r4, r8, lsl#1 @x1r = x0r - (x1r << 1)@
65 SUB r9, r5, r9, lsl#1 @x1i = x0i - (x1i << 1)
68 ADD r10, r6, r11, lsl#1 @x3i = x2r + (x3i << 1)@
69 SUB r11, r7, r1, lsl#1 @x3r = x2i - (x3r << 1)@
113 SUB r8, r4, r8, lsl #1 @x2r = x0r - (x2r << 1)@
114 SUB r9, r5, r9, lsl #1 @x2i = x0i - (x2i << 1)@
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-large-frame.ll | 14 ; CHECK: sub sp, sp, #4095, lsl #12
15 ; CHECK: sub sp, sp, #4095, lsl #12
16 ; CHECK: sub sp, sp, #1575, lsl #12
21 ; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
22 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
29 ; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
30 ; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
42 ; CHECK: add sp, sp, #4095, lsl #12
43 ; CHECK: add sp, sp, #4095, lsl #12
44 ; CHECK: add sp, sp, #1575, lsl #12
[all …]
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| D | arm64-movi.ll | 55 ; CHECK-NEXT: movk x0, #4660, lsl #32
56 ; CHECK-NEXT: movk x0, #43981, lsl #16
64 ; CHECK-NEXT: movk x0, #17185, lsl #16
100 ; CHECK: movk x0, #57005, lsl #16
107 ; CHECK: movk x0, #57005, lsl #48
114 ; CHECK: movk x0, #57005, lsl #32
129 ; CHECK: movk x0, #57005, lsl #16
136 ; CHECK: movk x0, #57005, lsl #16
137 ; CHECK: movk x0, #57005, lsl #48
144 ; CHECK: movk x0, #57005, lsl #48
[all …]
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| D | mul_pow2.ll | 8 ; CHECK: lsl w0, w0, #1
16 ; CHECK: add w0, w0, w0, lsl #1
24 ; CHECK: lsl w0, w0, #2
32 ; CHECK: add w0, w0, w0, lsl #2
41 ; CHECK: lsl {{w[0-9]+}}, w0, #3
50 ; CHECK: lsl w0, w0, #3
58 ; CHECK: add w0, w0, w0, lsl #3
69 ; CHECK: neg w0, w0, lsl #1
77 ; CHECK: sub w0, w0, w0, lsl #2
85 ; CHECK:neg w0, w0, lsl #2
[all …]
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| /external/llvm/test/CodeGen/ARM/ |
| D | mul_const.ll | 6 ; CHECK: add r0, r0, r0, lsl #3
14 ; CHECK: rsb r0, r0, r0, lsl #3
22 ; CHECK: add r0, r0, r0, lsl #2
30 ; CHECK: add r0, r0, r0, lsl #1
38 ; CHECK: add r0, r0, r0, lsl #1
39 ; CHECK: lsl{{.*}}#12
47 ; CHECK: add r0, r0, r0, lsl #3
56 ; CHECK: sub r0, r0, r0, lsl #3
64 ; CHECK: add r0, r0, r0, lsl #2
73 ; CHECK: sub r0, r0, r0, lsl #2
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | arm-shift-encoding.s | 6 ldr r0, [r0, r0, lsl #0]
7 ldr r0, [r0, r0, lsl #16]
17 @ CHECK: ldr r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x90,0xe7]
26 pld [r0, r0, lsl #0]
27 pld [r0, r0, lsl #16]
37 @ CHECK: [r0, r0, lsl #16] @ encoding: [0x00,0xf8,0xd0,0xf7]
46 str r0, [r0, r0, lsl #0]
47 str r0, [r0, r0, lsl #16]
57 @ CHECK: str r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x80,0xe7]
70 str r6, [r7], r8, lsl #0
[all …]
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | shifter_operand.ll | 8 ; A8: add r0, r0, r1, lsl r2
11 ; A9: add r0, r0, r1, lsl r2
34 ; A8: ldr r0, [r0, r2, lsl #2]
35 ; A8: ldr r1, [r1, r2, lsl #2]
37 ; lsl #2 is free
39 ; A9: ldr r0, [r0, r2, lsl #2]
40 ; A9: ldr r1, [r1, r2, lsl #2]
57 ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
58 ; A8: str [[REG]], [r0, r1, lsl #2]
61 ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
[all …]
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| /external/libxaac/decoder/armv8/ |
| D | ixheaacd_fft32x32_ld2_armv8.s | 354 ADD w10, w2, w6, lsl #1 //sum_0qr = mul_0qr + (mul_2qr << 1)
355 SUB w2 , w2, w6, lsl #1 //sum_1qr = mul_0qr - (mul_2qr << 1)
359 ADD w8 , w3, w7, lsl #1 //sum_0qi = mul_0qi + (mul_2qi << 1)
360 SUB w3 , w3, w7, lsl #1 //sum_1qi = mul_0qi - (mul_2qi << 1)
364 ADD w9 , w10, w6, lsl #1 //sum_0qr + (sum_2qr << 1)
365 SUB w10, w10, w6, lsl #1 //sum_0qr - (sum_2qr << 1)
366 ADD w6 , w2 , w5, lsl #1 //sum_1qr + (sum_3qi << 1)
367 SUB w2 , w2 , w5, lsl #1 //sum_1qr - (sum_3qi << 1)
373 ADD w5 , w8 , w7, lsl #1 //sum_0qi + (sum_2qi << 1)
374 SUB w8 , w8 , w7, lsl #1 //sum_0qi - (sum_2qi << 1)
[all …]
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