Searched refs:mtilea (Results 1 – 15 of 15) sorted by relevance
| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 156 surf_drm->mtilea = surf_ws->mtilea; in surf_winsys_to_drm()
197 surf_ws->mtilea = surf_drm->mtilea; in surf_drm_to_winsys()
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| D | radeon_drm_bo.c | 888 …md->mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MA… in radeon_bo_get_metadata()
922 args.tiling_flags |= (md->mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << in radeon_bo_set_metadata()
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| /external/libdrm/radeon/ |
| D | radeon_surface.c | 678 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
679 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
749 switch (surf->mtilea) { in eg_surface_sanity()
759 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
924 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
931 if (surf->mtilea > 8) { in eg_surface_best()
932 surf->mtilea = 8; in eg_surface_best()
1023 surf->mtilea = 1 << (log2_int(h_over_w) >> 1); in eg_surface_best()
1323 surf->mtilea = 1; in si_surface_sanity()
1402 …si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_s… in si_surface_sanity()
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| D | radeon_surface.h | 132 uint32_t mtilea; member
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_radeon_winsys.h | 197 uint32_t mtilea; member
241 unsigned mtilea; member
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| D | radv_image.c | 446 metadata->mtilea = surface->mtilea; in radv_init_metadata()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_video.c | 171 surfaces[i]->mtilea = surfaces[best_tiling]->mtilea; in rvid_join_surfaces()
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| D | radeon_winsys.h | 241 unsigned mtilea; member
325 unsigned mtilea:4; /* max 8 */ member
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| D | r600_texture.c | 295 metadata->mtilea = surface->mtilea; in r600_texture_init_metadata()
601 fmask.mtilea = rtex->surface.mtilea; in r600_texture_get_fmask_info()
914 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea, in r600_print_texture_info()
1262 surface.mtilea = metadata.mtilea; in r600_texture_from_handle()
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| D | radeon_uvd.c | 1387 assert(luma->mtilea == chroma->mtilea); in ruvd_set_dt_surfaces()
1391 …->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea)); in ruvd_set_dt_surfaces()
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| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_surface.c | 407 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) { in radv_amdgpu_winsys_surface_init()
413 AddrTileInfoIn.macroAspectRatio = surf->mtilea; in radv_amdgpu_winsys_surface_init()
475 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio; in radv_amdgpu_winsys_surface_init()
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| D | radv_amdgpu_bo.c | 272 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea)); in radv_amdgpu_winsys_bo_set_metadata()
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_surface.c | 439 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) { in amdgpu_surface_init()
447 AddrTileInfoIn.macroAspectRatio = surf->mtilea; in amdgpu_surface_init()
516 surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio; in amdgpu_surface_init()
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| D | amdgpu_bo.c | 623 md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_buffer_get_metadata()
652 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea)); in amdgpu_buffer_set_metadata()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | evergreen_state.c | 769 macro_aspect = tmp->surface.mtilea; in evergreen_create_sampler_view_custom()
1028 macro_aspect = rtex->surface.mtilea; in evergreen_init_color_surface()
1193 macro_aspect = rtex->surface.mtilea; in evergreen_init_depth_surface()
3395 mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea); in evergreen_dma_copy_tile()
3420 mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea); in evergreen_dma_copy_tile()
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