| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
21 LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
25 TRANSPOSE8x8_SH_SH(reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15, reg8, in vpx_idct16_1d_rows_msa()
31 DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); in vpx_idct16_1d_rows_msa()
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
35 reg8); in vpx_idct16_1d_rows_msa()
80 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vpx_idct16_1d_rows_msa()
86 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
96 TRANSPOSE8x8_SH_SH(reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14, reg0, in vpx_idct16_1d_rows_msa()
97 reg2, reg4, reg6, reg8, reg10, reg12, reg14); in vpx_idct16_1d_rows_msa()
[all …]
|
| /external/syslinux/core/ |
| D | regdump.inc | 42 .reg8:
50 loop .reg8
|
| /external/llvm/test/DebugInfo/ |
| D | dwarfdump-debug-frame-simple.test | 10 ; FRAMES-NEXT: DW_CFA_offset: reg8 -4
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| /external/syslinux/gpxe/src/drivers/net/rtl818x/ |
| D | rtl8185_rtl8225.c | 723 u16 reg8, reg9; in rtl8225x_rf_init() local
733 reg8 = rtl8225_read(dev, 8); in rtl8225x_rf_init()
738 if (reg8 != 0x588 || reg9 != 0x700) { in rtl8225x_rf_init()
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.h | 481 const CPURegister& reg8 = NoReg);
495 const CPURegister& reg8 = NoCPUReg);
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| D | assembler-aarch64.cc | 4755 const CPURegister& reg8) { in AreAliased() argument
4762 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
4794 const CPURegister& reg8) { in AreSameSizeAndType() argument
4803 match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| /external/elfutils/tests/ |
| D | run-addrcfi.sh | 31 return address in reg8
41 integer reg8 (%eip): location expression: call_frame_cfa plus_uconst(-4)
78 return address in reg8
88 integer reg8 (%eip): location expression: call_frame_cfa plus_uconst(-4)
140 integer reg8 (%r8): undefined
206 integer reg8 (%r8): undefined
310 integer reg8 (r8): undefined
1332 integer reg8 (r8): undefined
2360 integer reg8 (r8): undefined
3386 integer reg8 (%r8): same_value
[all …]
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 230 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
267 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
276 match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| D | assembler-arm64.h | 362 const CPURegister& reg8 = NoReg);
375 const CPURegister& reg8 = NoCPUReg);
|
| /external/libyuv/files/source/ |
| D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
900 reg8 = reg2 * const_0x4A; in ARGBToUVRow_MSA()
904 reg8 += reg4 * const_0x26; in ARGBToUVRow_MSA()
916 reg6 -= reg8; in ARGBToUVRow_MSA()
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
2693 reg8 = (v4i32)__msa_ilvr_h((v8i16)zero, (v8i16)vec1); in I444ToARGBRow_MSA()
2699 reg4 -= reg8 * vec_vr; in I444ToARGBRow_MSA()
2701 reg2 -= reg8 * vec_vg; in I444ToARGBRow_MSA()
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| /external/llvm/include/llvm/Support/ |
| D | Dwarf.def | 209 HANDLE_DW_OP(0x58, reg8)
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| /external/v8/src/x87/ |
| D | macro-assembler-x87.cc | 2498 Register reg8) { in AreAliased() argument
2501 reg7.is_valid() + reg8.is_valid(); in AreAliased()
2511 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-x87.h | 54 Register reg8 = no_reg);
|
| /external/v8/src/ia32/ |
| D | macro-assembler-ia32.cc | 2652 Register reg8) { in AreAliased() argument
2655 reg7.is_valid() + reg8.is_valid(); in AreAliased()
2665 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-ia32.h | 51 Register reg8 = no_reg);
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | big_alu.ll | 5 …eg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg …
13 %tmp6 = extractelement <4 x float> %reg8, i32 0
18 %tmp11 = extractelement <4 x float> %reg8, i32 0
23 %tmp16 = extractelement <4 x float> %reg8, i32 0
28 %tmp21 = extractelement <4 x float> %reg8, i32 0
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| /external/elfutils/libdw/ |
| D | known-dwarf.h | 528 DWARF_ONE_KNOWN_DW_OP (reg8, DW_OP_reg8) \
|
| /external/v8/src/arm/ |
| D | macro-assembler-arm.cc | 3742 Register reg8) { in AreAliased() argument
3745 reg7.is_valid() + reg8.is_valid(); in AreAliased()
3755 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-arm.h | 80 Register reg8 = no_reg);
|
| /external/v8/src/ppc/ |
| D | macro-assembler-ppc.cc | 4261 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
4265 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
4276 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-ppc.h | 70 Register reg8 = no_reg, Register reg9 = no_reg,
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| /external/v8/src/s390/ |
| D | macro-assembler-s390.cc | 5260 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
5264 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
5275 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| /external/v8/src/x64/ |
| D | macro-assembler-x64.cc | 5061 Register reg8) { in AreAliased() argument
5064 reg7.is_valid() + reg8.is_valid(); in AreAliased()
5074 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-x64.h | 75 Register reg8 = no_reg);
|
| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 6400 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
6404 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
6415 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
|