/external/llvm/test/MC/ARM/ |
D | fullfp16.s | 93 vcvt.u16.f16 s28, s28, #1 101 @ ARM: vcvt.u16.f16 s28, s28, #1 @ encoding: [0x67,0xe9,0xbf,0xee] 109 @ THUMB: vcvt.u16.f16 s28, s28, #1 @ encoding: [0xbf,0xee,0x67,0xe9] 153 vseleq.f16 s30, s28, s23 154 @ ARM: vseleq.f16 s30, s28, s23 @ encoding: [0x2b,0xf9,0x0e,0xfe] 155 @ THUMB: vseleq.f16 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xf9]
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D | fullfp16-neg.s | 71 vcvt.u16.f16 s28, s28, #1 113 vseleq.f16 s30, s28, s23
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D | fp-armv8.s | 72 vseleq.f32 s30, s28, s23 73 @ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x2b,0xfa,0x0e,0xfe]
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D | thumb-fp-armv8.s | 75 vseleq.f32 s30, s28, s23 76 @ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xfa]
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D | simple-fp-encoding.s | 366 vcvt.u16.f32 s28, s28, #1 384 @ CHECK: vcvt.u16.f32 s28, s28, #1 @ encoding: [0x67,0xea,0xbf,0xee]
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/external/clang/test/CodeGen/ |
D | arm-arguments.c | 145 struct s28 { _Complex char f0; }; argument 146 struct s28 f28() {} in f28()
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D | arm64-arguments.c | 106 struct s28 { _Complex char f0; }; struct 107 struct s28 f28() {} in f28()
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D | x86_32-arguments-darwin.c | 124 struct s28 { int a; int b[]; } f28(void) { while (1) {} } in f28() argument
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/external/llvm/test/MC/Disassembler/ARM/ |
D | fullfp16-thumb.txt | 70 # CHECK: vcvt.u16.f16 s28, s28, #1 112 # CHECK: vseleq.f16 s30, s28, s23
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D | fullfp16-arm.txt | 70 # CHECK: vcvt.u16.f16 s28, s28, #1 112 # CHECK: vseleq.f16 s30, s28, s23
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D | thumb-fp-armv8.txt | 94 # CHECK: vseleq.f32 s30, s28, s23
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D | fp-armv8.txt | 90 # CHECK: vseleq.f32 s30, s28, s23
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D | fp-encoding.txt | 227 # CHECK: vstmdbeq r12!, {s25, s26, s27, s28}
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/external/swiftshader/third_party/subzero/src/ |
D | IceRegistersARM32.def | 65 X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s28, d14, q7)) \ 86 X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d14, q7, s28, s29)) \ 114 …X(Reg_q7, 7, "q7", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q7, d14, d15, s28, s29, s30…
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/external/llvm/test/CodeGen/AArch64/ |
D | remat-float0.ll | 15 …7},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s3…
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/external/capstone/suite/MC/ARM/ |
D | simple-fp-encoding.s.cs | 150 0x67,0xea,0xbf,0xee = vcvt.u16.f32 s28, s28, #1
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D | fp-armv8.s.cs | 30 0x2b,0xfa,0x0e,0xfe = vseleq.f32 s30, s28, s23
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D | thumb-fp-armv8.s.cs | 30 0x0e,0xfe,0x2b,0xfa = vseleq.f32 s30, s28, s23
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/external/vixl/test/aarch64/ |
D | test-api-aarch64.cc | 180 VIXL_CHECK(AreConsecutive(s26, s27, s28, s29)); in TEST() 208 VIXL_CHECK(!AreConsecutive(s28, s30, NoVReg, NoVReg)); in TEST()
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/external/valgrind/none/tests/arm/ |
D | vfp.c | 1587 TESTINSN_un_f32("vabs.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); in main() 1609 TESTINSN_un_f32("vneg.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); in main() 1631 TESTINSN_un_f32("vmov.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); in main() 1653 TESTINSN_un_f32("vsqrt.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); in main() 1720 TESTINSN_cvt_f64_i32("vcvt.f64.u32 d12, s28", d12, s28, f2u(5.00003245)); in main() 1728 TESTINSN_cvt_f64_i32("vcvt.f64.s32 d12, s28", d12, s28, f2u(5.00003245)); in main() 1846 TESTINSN_cmp_f32("vcmp.f32 s7, s28", s7, f2u(425.5), s28, f2u(-456.3)); in main() 1855 TESTINSN_cmp_f32("vcmp.f32 s7, s28", s7, f2u(INFINITY), s28, f2u(-8567.456)); in main() 1864 TESTINSN_cmp_f32("vcmpe.f32 s7, s28", s7, f2u(425.5), s28, f2u(-456.3)); in main() 1872 TESTINSN_cmp_f32("vcmpe.f32 s7, s28", s7, f2u(INFINITY), s28, f2u(-8567.456)); in main() [all …]
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/external/llvm/test/CodeGen/MIR/ARM/ |
D | ARMLoadStoreDBG.mir | 97 '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
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D | sched-it-debug-nodes.mir | 108 '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
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/external/v8/src/arm/ |
D | simulator-arm.h | 123 s24, s25, s26, s27, s28, s29, s30, s31, enumerator
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/external/v8/benchmarks/ |
D | regexp.js | 209 var s28 = computeInputVariants('k',78); 246 s28[i].replace(/./, '');
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/external/capstone/suite/MC/AArch64/ |
D | basic-a64-instructions.s.cs | 826 0x9b,0x03,0x24,0x9e = fcvtas x27, s28 1203 0xfd,0xf3,0x5f,0x2d = ldp s29, s28, [sp, #252] 1222 0xfd,0xf3,0xdf,0x2c = ldp s29, s28, [sp], #252 1241 0xfd,0xf3,0xdf,0x2d = ldp s29, s28, [sp, #252]! 1257 0xfd,0xf3,0x5f,0x2c = ldnp s29, s28, [sp, #252]
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