Home
last modified time | relevance | path

Searched refs:s28 (Results 1 – 25 of 43) sorted by relevance

12

/external/llvm/test/MC/ARM/
Dfullfp16.s93 vcvt.u16.f16 s28, s28, #1
101 @ ARM: vcvt.u16.f16 s28, s28, #1 @ encoding: [0x67,0xe9,0xbf,0xee]
109 @ THUMB: vcvt.u16.f16 s28, s28, #1 @ encoding: [0xbf,0xee,0x67,0xe9]
153 vseleq.f16 s30, s28, s23
154 @ ARM: vseleq.f16 s30, s28, s23 @ encoding: [0x2b,0xf9,0x0e,0xfe]
155 @ THUMB: vseleq.f16 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xf9]
Dfullfp16-neg.s71 vcvt.u16.f16 s28, s28, #1
113 vseleq.f16 s30, s28, s23
Dfp-armv8.s72 vseleq.f32 s30, s28, s23
73 @ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x2b,0xfa,0x0e,0xfe]
Dthumb-fp-armv8.s75 vseleq.f32 s30, s28, s23
76 @ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xfa]
Dsimple-fp-encoding.s366 vcvt.u16.f32 s28, s28, #1
384 @ CHECK: vcvt.u16.f32 s28, s28, #1 @ encoding: [0x67,0xea,0xbf,0xee]
/external/clang/test/CodeGen/
Darm-arguments.c145 struct s28 { _Complex char f0; }; argument
146 struct s28 f28() {} in f28()
Darm64-arguments.c106 struct s28 { _Complex char f0; }; struct
107 struct s28 f28() {} in f28()
Dx86_32-arguments-darwin.c124 struct s28 { int a; int b[]; } f28(void) { while (1) {} } in f28() argument
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-thumb.txt70 # CHECK: vcvt.u16.f16 s28, s28, #1
112 # CHECK: vseleq.f16 s30, s28, s23
Dfullfp16-arm.txt70 # CHECK: vcvt.u16.f16 s28, s28, #1
112 # CHECK: vseleq.f16 s30, s28, s23
Dthumb-fp-armv8.txt94 # CHECK: vseleq.f32 s30, s28, s23
Dfp-armv8.txt90 # CHECK: vseleq.f32 s30, s28, s23
Dfp-encoding.txt227 # CHECK: vstmdbeq r12!, {s25, s26, s27, s28}
/external/swiftshader/third_party/subzero/src/
DIceRegistersARM32.def65 X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s28, d14, q7)) \
86 X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d14, q7, s28, s29)) \
114 …X(Reg_q7, 7, "q7", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q7, d14, d15, s28, s29, s30…
/external/llvm/test/CodeGen/AArch64/
Dremat-float0.ll15 …7},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s3…
/external/capstone/suite/MC/ARM/
Dsimple-fp-encoding.s.cs150 0x67,0xea,0xbf,0xee = vcvt.u16.f32 s28, s28, #1
Dfp-armv8.s.cs30 0x2b,0xfa,0x0e,0xfe = vseleq.f32 s30, s28, s23
Dthumb-fp-armv8.s.cs30 0x0e,0xfe,0x2b,0xfa = vseleq.f32 s30, s28, s23
/external/vixl/test/aarch64/
Dtest-api-aarch64.cc180 VIXL_CHECK(AreConsecutive(s26, s27, s28, s29)); in TEST()
208 VIXL_CHECK(!AreConsecutive(s28, s30, NoVReg, NoVReg)); in TEST()
/external/valgrind/none/tests/arm/
Dvfp.c1587 TESTINSN_un_f32("vabs.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); in main()
1609 TESTINSN_un_f32("vneg.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); in main()
1631 TESTINSN_un_f32("vmov.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); in main()
1653 TESTINSN_un_f32("vsqrt.f32 s28, s7", s28, s7, i32, f2u(-4856.234)); in main()
1720 TESTINSN_cvt_f64_i32("vcvt.f64.u32 d12, s28", d12, s28, f2u(5.00003245)); in main()
1728 TESTINSN_cvt_f64_i32("vcvt.f64.s32 d12, s28", d12, s28, f2u(5.00003245)); in main()
1846 TESTINSN_cmp_f32("vcmp.f32 s7, s28", s7, f2u(425.5), s28, f2u(-456.3)); in main()
1855 TESTINSN_cmp_f32("vcmp.f32 s7, s28", s7, f2u(INFINITY), s28, f2u(-8567.456)); in main()
1864 TESTINSN_cmp_f32("vcmpe.f32 s7, s28", s7, f2u(425.5), s28, f2u(-456.3)); in main()
1872 TESTINSN_cmp_f32("vcmpe.f32 s7, s28", s7, f2u(INFINITY), s28, f2u(-8567.456)); in main()
[all …]
/external/llvm/test/CodeGen/MIR/ARM/
DARMLoadStoreDBG.mir97 '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
Dsched-it-debug-nodes.mir108 '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
/external/v8/src/arm/
Dsimulator-arm.h123 s24, s25, s26, s27, s28, s29, s30, s31, enumerator
/external/v8/benchmarks/
Dregexp.js209 var s28 = computeInputVariants('k',78);
246 s28[i].replace(/./, '');
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs826 0x9b,0x03,0x24,0x9e = fcvtas x27, s28
1203 0xfd,0xf3,0x5f,0x2d = ldp s29, s28, [sp, #252]
1222 0xfd,0xf3,0xdf,0x2c = ldp s29, s28, [sp], #252
1241 0xfd,0xf3,0xdf,0x2d = ldp s29, s28, [sp, #252]!
1257 0xfd,0xf3,0x5f,0x2c = ldnp s29, s28, [sp, #252]

12