| /external/llvm/test/CodeGen/AMDGPU/ |
| D | promote-alloca-to-lds-select.ll | 68 ; CHECK: %select1 = select i1 undef, i32 addrspace(3)* %select0, i32 addrspace(3)* %ptr2
69 ; CHECK: store i32 0, i32 addrspace(3)* %select1, align 4
76 %select1 = select i1 undef, i32* %select0, i32* %ptr2
77 store i32 0, i32* %select1, align 4
97 %select1 = select i1 undef, i32* %phi.ptr, i32* %ptr1
98 store i32 0, i32* %select1, align 4
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstSimplify/ |
| D | rem.ll | 3 define i32 @select1(i32 %x, i1 %b) {
4 ; CHECK: @select1
|
| D | compare.ll | 172 define i1 @select1(i1 %cond) {
173 ; CHECK: @select1
|
| /external/llvm/test/Transforms/InstSimplify/ |
| D | rem.ll | 4 define i32 @select1(i32 %x, i1 %b) {
5 ; CHECK-LABEL: @select1(
|
| D | compare.ll | 455 define i1 @select1(i1 %cond) {
456 ; CHECK-LABEL: @select1(
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_perfcounter.c | 495 unsigned select1 = in si_pc_emit_select() local
497 radeon_set_uconfig_reg_seq(cs, select1, count); in si_pc_emit_select()
508 unsigned select1, select1_count; in si_pc_emit_select() local
518 select1 = regs->select0 + 4 * regs->num_counters; in si_pc_emit_select()
520 radeon_set_uconfig_reg_seq(cs, select1, select1_count); in si_pc_emit_select()
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-minmaxv.ll | 295 …%rdx.minmax.select1 = select <4 x i1> %rdx.minmax.cmp, <4 x float> %rdx.minmax.select, <4 x float>…
296 …%rdx.shuf1 = shufflevector <4 x float> %rdx.minmax.select1, <4 x float> undef, <4 x i32> <i32 1, i…
297 %rdx.minmax.cmp1 = fcmp fast oge <4 x float> %rdx.minmax.select1, %rdx.shuf1
299 %rdx.minmax.select1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 0
300 %rdx.shuf1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 1
301 %r = select i1 %rdx.minmax.cmp1.elt, float %rdx.minmax.select1.elt, float %rdx.shuf1.elt
311 …%rdx.minmax.select1 = select <4 x i1> %rdx.minmax.cmp, <4 x float> %rdx.minmax.select, <4 x float>…
312 …%rdx.shuf1 = shufflevector <4 x float> %rdx.minmax.select1, <4 x float> undef, <4 x i32> <i32 1, i…
313 %rdx.minmax.cmp1 = fcmp fast ole <4 x float> %rdx.minmax.select1, %rdx.shuf1
315 %rdx.minmax.select1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 0
[all …]
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| D | cast-mul-select.ll | 16 define i32 @select1(i1 %cond, i32 %x, i32 %y, i32 %z) {
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | cast-mul-select.ll | 16 define i32 @select1(i1 %cond, i32 %x, i32 %y, i32 %z) {
|
| /external/tensorflow/tensorflow/compiler/xla/tests/ |
| D | tuple_test.cc | 382 auto select1 = in XLA_TEST_F() local
385 builder.Select(builder.GetTupleElement(pred_tuple, 1), tuple21, select1); in XLA_TEST_F()
|
| /external/tensorflow/tensorflow/python/kernel_tests/ |
| D | control_flow_ops_py_test.py | 1470 select1 = variables.Variable([3.0, 4.0, 5.0])
1478 ns1 = state_ops.scatter_update(select1, j, 10.0)
1489 result1 = select1.eval()
|
| /external/swiftshader/src/Reactor/ |
| D | LLVMReactor.cpp | 3269 …RValue<UShort8> Swizzle(RValue<UShort8> x, char select0, char select1, char select2, char select3,… in Swizzle() argument
3275 select1 + 0, in Swizzle()
3276 select1 + 1, in Swizzle()
|
| D | Reactor.hpp | 983 …RValue<UShort8> Swizzle(RValue<UShort8> x, char select0, char select1, char select2, char select3,…
|
| D | SubzeroReactor.cpp | 4330 …RValue<UShort8> Swizzle(RValue<UShort8> x, char select0, char select1, char select2, char select3,… in Swizzle() argument
|