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Searched refs:setOpcode (Results 1 – 25 of 84) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86MCInstLower.cpp219 OutMI.setOpcode(NewOpc); in LowerSubReg32_Op0()
224 OutMI.setOpcode(NewOpc); in LowerUnaryToTwoAddr()
246 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
297 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
302 OutMI.setOpcode(MI->getOpcode()); in Lower()
400 OutMI.setOpcode(Opcode); in Lower()
408 OutMI.setOpcode(X86::RET); in Lower()
426 OutMI.setOpcode(Opcode); in Lower()
434 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; in Lower()
435 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; in Lower()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp702 Result.setOpcode(Hexagon::V4_SA1_inc); in deriveSubInst()
708 Result.setOpcode(Hexagon::V4_SA1_dec); in deriveSubInst()
714 Result.setOpcode(Hexagon::V4_SA1_addsp); in deriveSubInst()
720 Result.setOpcode(Hexagon::V4_SA1_addi); in deriveSubInst()
727 Result.setOpcode(Hexagon::V4_SA1_addrx); in deriveSubInst()
733 Result.setOpcode(Hexagon::V4_SS2_allocframe); in deriveSubInst()
738 Result.setOpcode(Hexagon::V4_SA1_zxtb); in deriveSubInst()
743 Result.setOpcode(Hexagon::V4_SA1_and1); in deriveSubInst()
749 Result.setOpcode(Hexagon::V4_SA1_cmpeqi); in deriveSubInst()
758 Result.setOpcode(Hexagon::V4_SA1_combine1i); in deriveSubInst()
[all …]
DHexagonMCCompound.cpp220 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
233 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
247 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
260 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
273 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
291 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
310 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
322 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
333 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp265 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
289 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
308 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
321 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
334 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h); in HexagonProcessInstruction()
336 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l); in HexagonProcessInstruction()
345 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h); in HexagonProcessInstruction()
347 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l); in HexagonProcessInstruction()
357 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h); in HexagonProcessInstruction()
359 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l); in HexagonProcessInstruction()
[all …]
/external/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp281 Inst.setOpcode(XCore::STW_2rus); in Decode2OpInstructionFail()
284 Inst.setOpcode(XCore::LDW_2rus); in Decode2OpInstructionFail()
287 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
290 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
293 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
296 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
299 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
302 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
305 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
308 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
[all …]
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp268 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
296 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
347 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
390 OutMI.setOpcode(MI->getOpcode()); in Lower()
444 OutMI.setOpcode(NewOpc); in Lower()
458 OutMI.setOpcode(NewOpc); in Lower()
473 OutMI.setOpcode(Opcode); in Lower()
481 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
488 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
497 OutMI.setOpcode(getRetOpcode(Subtarget)); in Lower()
[all …]
/external/annotation-tools/asmx/test/conform/org/objectweb/asm/tree/
DUnitTest.java16 iin.setOpcode(SIPUSH); in testNodes()
21 vn.setOpcode(ASTORE); in testNodes()
26 tin.setOpcode(CHECKCAST); in testNodes()
31 fn.setOpcode(PUTSTATIC); in testNodes()
39 mn.setOpcode(INVOKESPECIAL); in testNodes()
44 jn.setOpcode(IFEQ); in testNodes()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMAsmPrinter.cpp983 BrInst.setOpcode(ARM::t2B); in EmitJump2Table()
1044 TmpInst.setOpcode(Opcode); in EmitPatchedInstruction()
1213 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR in EmitInstruction()
1227 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR in EmitInstruction()
1244 TmpInst.setOpcode(ARM::MOVr); in EmitInstruction()
1256 TmpInst.setOpcode(ARM::BX); in EmitInstruction()
1266 TmpInst.setOpcode(ARM::tMOVr); in EmitInstruction()
1276 TmpInst.setOpcode(ARM::tBX); in EmitInstruction()
1289 TmpInst.setOpcode(ARM::MOVr); in EmitInstruction()
1301 TmpInst.setOpcode(ARM::MOVr); in EmitInstruction()
[all …]
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp755 NewInst.setOpcode(MCI.getOpcode()); in canonicalizeImmediates()
1463 TmpInst.setOpcode(opCode); in makeCombineInst()
1539 Inst.setOpcode(Hexagon::A2_addi); in processInstruction()
1571 Inst.setOpcode(Hexagon::C2_cmpgti); in processInstruction()
1585 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1593 Inst.setOpcode(Hexagon::C2_cmpgtui); in processInstruction()
1609 Inst.setOpcode(Hexagon::A2_combinew); in processInstruction()
1624 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in processInstruction()
1640 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) in processInstruction()
1655 Inst.setOpcode(Hexagon::V6_vcombine); in processInstruction()
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/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp434 MOVI.setOpcode(AArch64::MOVIv2d_ns); in EmitFMov0()
443 FMov.setOpcode(AArch64::FMOVWSr); in EmitFMov0()
448 FMov.setOpcode(AArch64::FMOVXDr); in EmitFMov0()
493 TmpInst.setOpcode(AArch64::BR); in EmitInstruction()
502 TmpInst.setOpcode(AArch64::B); in EmitInstruction()
526 Adrp.setOpcode(AArch64::ADRP); in EmitInstruction()
532 Ldr.setOpcode(AArch64::LDRXui); in EmitInstruction()
540 Add.setOpcode(AArch64::ADDXri); in EmitInstruction()
550 TLSDescCall.setOpcode(AArch64::TLSDESCCALL); in EmitInstruction()
555 Blr.setOpcode(AArch64::BLR); in EmitInstruction()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1876 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
1879 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
1882 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
1885 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
1888 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
1891 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
1894 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
1897 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
1900 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
1903 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
[all …]
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp608 MI.setOpcode(Mips::BOVC); in DecodeAddiGroupBranch()
611 MI.setOpcode(Mips::BEQC); in DecodeAddiGroupBranch()
614 MI.setOpcode(Mips::BEQZALC); in DecodeAddiGroupBranch()
636 MI.setOpcode(Mips::BOVC_MMR6); in DecodePOP35GroupBranchMMR6()
642 MI.setOpcode(Mips::BEQC_MMR6); in DecodePOP35GroupBranchMMR6()
648 MI.setOpcode(Mips::BEQZALC_MMR6); in DecodePOP35GroupBranchMMR6()
678 MI.setOpcode(Mips::BNVC); in DecodeDaddiGroupBranch()
681 MI.setOpcode(Mips::BNEC); in DecodeDaddiGroupBranch()
684 MI.setOpcode(Mips::BNEZALC); in DecodeDaddiGroupBranch()
706 MI.setOpcode(Mips::BNVC_MMR6); in DecodePOP37GroupBranchMMR6()
[all …]
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp848 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
860 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
870 TmpInst.setOpcode(PPC::DCBTST); in ProcessInstruction()
879 TmpInst.setOpcode(PPC::LA); in ProcessInstruction()
888 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
897 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction()
906 TmpInst.setOpcode(PPC::ADDIC); in ProcessInstruction()
915 TmpInst.setOpcode(PPC::ADDICo); in ProcessInstruction()
927 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); in ProcessInstruction()
941 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); in ProcessInstruction()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp70 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
73 Inst.setOpcode(Mips::DSRL32); in LowerLargeShift()
76 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
79 Inst.setOpcode(Mips::DROTR32); in LowerLargeShift()
82 Inst.setOpcode(Mips::DSLL32_MM64R6); in LowerLargeShift()
85 Inst.setOpcode(Mips::DSRL32_MM64R6); in LowerLargeShift()
88 Inst.setOpcode(Mips::DSRA32_MM64R6); in LowerLargeShift()
91 Inst.setOpcode(Mips::DROTR32_MM64R6); in LowerLargeShift()
111 InstIn.setOpcode(Mips::DINSU); in LowerDins()
117 InstIn.setOpcode(Mips::DINSM); in LowerDins()
[all …]
DMipsTargetStreamer.cpp132 TmpInst.setOpcode(Opcode); in emitR()
141 TmpInst.setOpcode(Opcode); in emitRX()
161 TmpInst.setOpcode(Opcode); in emitII()
172 TmpInst.setOpcode(Opcode); in emitRRX()
1017 TmpInst.setOpcode(Mips::LUi); in emitDirectiveCpLoad()
1029 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad()
1042 TmpInst.setOpcode(Mips::ADDu); in emitDirectiveCpLoad()
1140 Inst.setOpcode(Mips::OR); in emitDirectiveCpreturn()
1145 Inst.setOpcode(Mips::LD); in emitDirectiveCpreturn()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp4791 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
4792 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
4801 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
4805 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
4816 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
4823 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
6833 TmpInst.setOpcode(Opcode); in processInstruction()
6851 TmpInst.setOpcode(Opcode); in processInstruction()
6869 TmpInst.setOpcode(ARM::ADR); in processInstruction()
6906 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
[all …]
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp105 TmpInst0.setOpcode(Mips::JALR64); in emitPseudoIndirectBranch()
109 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
113 TmpInst0.setOpcode(Mips::JR_MM); in emitPseudoIndirectBranch()
116 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch()
754 I.setOpcode(Mips::JAL); in EmitJal()
763 I.setOpcode(Opcode); in EmitInstrReg()
782 I.setOpcode(Opcode); in EmitInstrRegReg()
792 I.setOpcode(Opcode); in EmitInstrRegRegReg()
DMipsMCInstLower.cpp217 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
231 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
271 OutMI.setOpcode(MI->getOpcode()); in Lower()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1632 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
1635 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
1638 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
1641 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
1644 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
1647 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
1650 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
1653 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
1656 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
1659 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrInfo.cpp38 NopInst.setOpcode(ARM::HINT); in getNoopForMachoTarget()
43 NopInst.setOpcode(ARM::MOVr); in getNoopForMachoTarget()
/external/annotation-tools/asmx/src/org/objectweb/asm/tree/
DVarInsnNode.java70 public void setOpcode(final int opcode) { in setOpcode() method in VarInsnNode
DIntInsnNode.java64 public void setOpcode(final int opcode) { in setOpcode() method in IntInsnNode
DTypeInsnNode.java67 public void setOpcode(final int opcode) { in setOpcode() method in TypeInsnNode
DJumpInsnNode.java73 public void setOpcode(final int opcode) { in setOpcode() method in JumpInsnNode
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXMCInstLower.cpp25 OutMI.setOpcode(MI->getOpcode()); in LowerPTXMachineInstrToMCInst()

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