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Searched refs:spill (Results 1 – 25 of 230) sorted by relevance

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/external/libunwind/src/ia64/
Dgetcontext.S51 st8.spill [r2] = r1, (SC_FLAGS - GR(1)) // M3
66 st8.spill [r2] = r12, (GR(4) - GR(12)) // M3
70 stf.spill [r3] = f2 // M2
71 stf.spill [r8] = f16 // M3
76 stf.spill [r9] = f24, (FR(31) - FR(24)) // M2
80 stf.spill [r9] = f31 // M2
81 st8.spill [r2] = r4, (GR(5) - GR(4)) // M3, bank 1
85 .mem.offset 0,0; st8.spill [r2] = r5, (GR(6) - GR(5)) // M4, bank 0
86 .mem.offset 8,0; st8.spill [r3] = r7, (BR(0) - GR(7)) // M3, bank 0
90 st8.spill [r2] = r6, (BR(1) - GR(6)) // M2, bank 1
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-vector-list-spill.ll3 ; FIXME: We should not generate ld/st for such register spill/fill, because the
5 ; spill/fill algorithm is optimized, this test case may not be triggered. And
7 define i32 @spill.DPairReg(i32* %arg1, i32 %arg2) {
8 ; CHECK-LABEL: spill.DPairReg:
27 define i16 @spill.DTripleReg(i16* %arg1, i32 %arg2) {
28 ; CHECK-LABEL: spill.DTripleReg:
47 define i16 @spill.DQuadReg(i16* %arg1, i32 %arg2) {
48 ; CHECK-LABEL: spill.DQuadReg:
67 define i32 @spill.QPairReg(i32* %arg1, i32 %arg2) {
68 ; CHECK-LABEL: spill.QPairReg:
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/ia64/
Dunix.S308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 16
324 st8.spill [r17] = in1, 16
[all …]
/external/libffi/src/ia64/
Dunix.S308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 16
324 st8.spill [r17] = in1, 16
[all …]
/external/python/cpython3/Modules/_ctypes/libffi/src/ia64/
Dunix.S308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 16
324 st8.spill [r17] = in1, 16
[all …]
/external/llvm/test/CodeGen/X86/
Dpr27681.mir19 - { id: 0, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%esi' }
20 - { id: 1, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%edi' }
21 - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%ebx' }
22 - { id: 3, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%ebp' }
24 - { id: 0, type: spill-slot, offset: -53, size: 1, alignment: 1 }
25 - { id: 1, type: spill-slot, offset: -48, size: 4, alignment: 4 }
26 - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
Dsetjmp-spills.ll11 ; Test that llc avoids reusing spill slots in functions that call
20 ; spill slot.
39 ; Again, keep enough variables live that they need spill slots. Since
41 ; compiler should not reuse the spill slots. longjmp() can return to
42 ; where the first spill slots were still live.
Dpop-stack-cleanup.ll52 define void @spill(i32 inreg %a, i32 inreg %b, i32 inreg %c) minsize nounwind {
53 ; CHECK-LABEL: spill:
63 call void @spill(i32 %a, i32 %b, i32 %c)
Dhoist-spill-lpad.ll3 ; PR27612. The following spill is hoisted from two locations: the fall
5 ; exception. If it is not hoisted before the call, the spill will be
/external/llvm/test/CodeGen/XCore/
Depilogue_prologue.ll8 ; FP + small frame: spill FP+SR = entsp 2
29 ; FP + small frame: spill FP+SR+R0+LR = entsp 3 + extsp 1
45 ; !FP + small frame: spill R0+LR = entsp 2
62 ; FP + large frame: spill FP+SR = entsp 2 + 100000
83 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
102 ; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000 + extsp 1
155 ; !FP + large frame: spill SR+SR+R4+LR = entsp 4 + 200000
209 ; FP + large frame: spill FP+SR+LR = entsp 2 + 256 + extsp 1
223 ; !FP + large frame: spill SR+SR+LR = entsp 3 + 256
237 ; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1
[all …]
Dllvm-intrinsics.ll154 ; FP: spill FP+SR+R0:1+R4:9 = entsp 2+2+6
155 ; But we dont actually spill or restore R0:1
176 ; !FP: spill R0:1+R4:10 = entsp 2+7
177 ; But we dont actually spill or restore R0:1
201 ; FP: spill FP+SR+R0:1+R4:9+LR = entsp 2+2+6 + extsp 1
202 ; But we dont actually spill or restore R0:1
226 ; !FP: spill R0:1+R4:10+LR = entsp 2+7+1
227 ; But we dont actually spill or restore R0:1
252 ; FP: spill FP+SR+R0:1+R4:9 = entsp 2+2+6
253 ; We dont spill R0:1
[all …]
Dscavenging.ll70 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
76 ; scavenge r4 using SR spill slot
82 ; scavenge r5 using SR spill slot
/external/llvm/test/CodeGen/MIR/Mips/
Dmemory-operands.mir40 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
72 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
74 - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4,
76 - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4,
/external/libunwind/tests/
Dia64-test-nat-asm.S108 stf.spill [sp] = f2, -16
188 st8.spill [sp] = r4, -16
225 st8.spill [sp] = r6, -16;;
263 st8.spill [sp] = r6, -16;;
305 st8.spill [sp] = r6, -16;;
348 st8.spill [sp] = r6, -16;;
392 st8.spill [sp] = r7 // save r7 in the scratch stack space
/external/llvm/test/CodeGen/MIR/X86/
Dspill-slot-fixed-stack-objects.mir22 # CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
24 - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
Dstack-objects.mir26 # CHECK-NEXT: - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
30 - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
/external/llvm/test/CodeGen/Hexagon/
Davoid-predspill-calleesaved.ll6 ; We expect to spill p0 into a general-purpose register and keep it there,
7 ; without adding an extra spill of that register.
/external/llvm/test/CodeGen/ARM/
Dvarargs-spill-stack-align-nacl.ll9 ; stack. A varargs function must therefore spill rN-r3 just below the
12 ; This test checks for a bug in which a gap was left between the spill
D2010-05-18-LocalAllocCrash.ll3 ;; This test would spill %R4 before the call to zz, but it forgot to move the
4 ; 'last use' marker to the spill.
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
D2010-05-18-LocalAllocCrash.ll3 ;; This test would spill %R4 before the call to zz, but it forgot to move the
4 ; 'last use' marker to the spill.
/external/llvm/test/CodeGen/Thumb2/
Daligned-spill.ll7 ; This function is forced to spill a double.
8 ; Verify that the spill slot is properly aligned.
33 ; Since the spill slot is only 8 bytes, technically it would be fine to only
/external/llvm/test/CodeGen/MIR/ARM/
Dcfi-same-value.mir25 - { id: 1, type: spill-slot, offset: -4, size: 4, alignment: 4,
27 - { id: 2, type: spill-slot, offset: -8, size: 4, alignment: 4,
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg.ll18 ; allocator will choose $f12 and $f13 to avoid the spill/reload.
21 ; will be forced to spill/reload either %a or %0.
/external/llvm/lib/CodeGen/
DSpiller.h31 virtual void spill(LiveRangeEdit &LRE) = 0;
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DSpiller.h29 virtual void spill(LiveRangeEdit &LRE) = 0;

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