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Searched refs:srsra (Results 1 – 24 of 24) sorted by relevance

/external/capstone/suite/MC/AArch64/
Dneon-simd-shift.s.cs44 0x20,0x34,0x0d,0x0f = srsra v0.8b, v1.8b, #3
45 0x20,0x34,0x1d,0x0f = srsra v0.4h, v1.4h, #3
46 0x20,0x34,0x3d,0x0f = srsra v0.2s, v1.2s, #3
47 0x20,0x34,0x0d,0x4f = srsra v0.16b, v1.16b, #3
48 0x20,0x34,0x1d,0x4f = srsra v0.8h, v1.8h, #3
49 0x20,0x34,0x3d,0x4f = srsra v0.4s, v1.4s, #3
50 0x20,0x34,0x7d,0x4f = srsra v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s.cs8 0x6f,0x35,0x6d,0x5f = srsra d15, d11, #19
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s123 srsra v0.8b, v1.8b, #3
124 srsra v0.4h, v1.4h, #3
125 srsra v0.2s, v1.2s, #3
126 srsra v0.16b, v1.16b, #3
127 srsra v0.8h, v1.8h, #3
128 srsra v0.4s, v1.4s, #3
129 srsra v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s50 srsra d15, d11, #19
Darm64-advsimd.s1376 srsra d0, d0, #1 define
1425 ; CHECK: srsra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x5f]
1538 srsra.8b v0, v0, #1
1539 srsra.16b v0, v0, #2
1540 srsra.4h v0, v0, #3
1541 srsra.8h v0, v0, #4
1542 srsra.2s v0, v0, #5
1543 srsra.4s v0, v0, #6
1544 srsra.2d v0, v0, #7
1710 ; CHECK: srsra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x0f]
[all …]
Dneon-diagnostics.s1576 srsra v0.8b, v1.8h, #3
1577 srsra v0.4h, v1.4s, #3
1578 srsra v0.2s, v1.2d, #3
1579 srsra v0.16b, v1.16b, #9
1580 srsra v0.8h, v1.8h, #17
1581 srsra v0.4s, v1.4s, #33
1582 srsra v0.2d, v1.2d, #65
4973 srsra d15, d11, #99
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt828 # CHECK: srsra v0.8b, v1.8b, #3
829 # CHECK: srsra v0.4h, v1.4h, #3
830 # CHECK: srsra v0.2s, v1.2s, #3
831 # CHECK: srsra v0.16b, v1.16b, #3
832 # CHECK: srsra v0.8h, v1.8h, #3
833 # CHECK: srsra v0.4s, v1.4s, #3
834 # CHECK: srsra v0.2d, v1.2d, #3
1852 # CHECK: srsra d15, d11, #19
Darm64-advsimd.txt1831 # CHECK: srsra d0, d0, #0x3f
2113 # CHECK: srsra.8b v0, v0, #0x7
2114 # CHECK: srsra.16b v0, v0, #0x6
2115 # CHECK: srsra.4h v0, v0, #0xd
2116 # CHECK: srsra.8h v0, v0, #0xc
2117 # CHECK: srsra.2s v0, v0, #0x1b
2118 # CHECK: srsra.4s v0, v0, #0x1a
2119 # CHECK: srsra.2d v0, v0, #0x39
/external/llvm/test/CodeGen/AArch64/
Darm64-vshift.ll1445 ;CHECK: srsra.8b v0, {{v[0-9]+}}, #1
1455 ;CHECK: srsra.4h v0, {{v[0-9]+}}, #1
1465 ;CHECK: srsra.2s v0, {{v[0-9]+}}, #1
1475 ;CHECK: srsra.16b v0, {{v[0-9]+}}, #1
1485 ;CHECK: srsra.8h v0, {{v[0-9]+}}, #1
1495 ;CHECK: srsra.4s v0, {{v[0-9]+}}, #1
1505 ;CHECK: srsra.2d v0, {{v[0-9]+}}, #1
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp28620 srsra d5, d28, #1 fb6bd604b83bfb851cbe1c439ce285fa 5a0ae8799eadc8c9023619cf0ccbf4ab 00000000000…
28621 srsra d5, d28, #32 976c2f95dcef65994633a260d37e67e0 87bb84d0cd04724641473c0f0fa44d22 0000000000…
28622 srsra d5, d28, #64 b8a21383887898dce1c81be83cfc856c dc43edce054d982fad02df6e4b9d217a 0000000000…
28626 srsra v6.2d, v27.2d, #1 c3fd232d57b4def4a9ebe37803fee3b2 cfccce146bed89962749ac95ddf534f1 abe3…
28627 srsra v6.2d, v27.2d, #32 56ce892d9eb8413d71e361c0134d8303 245f3c4d877f23f1aed4a740ee942fed 56c…
28628 srsra v6.2d, v27.2d, #64 d49c53e7dbaa8361999b97e64c101614 fce8e678b078f3df2d183200401e7560 d49…
28629 srsra v6.4s, v27.4s, #1 9e48e13a6e6c034280f5e5ca0f25fac4 b8452d7547b85a4103f4aeb73473662c 7a6b…
28630 srsra v6.4s, v27.4s, #16 13b09407b5dc21be87cfac4cba6d92f5 b7587024ab1fb6f7914a7a432973602f 13b…
28631 srsra v6.4s, v27.4s, #32 94b5cb2f13db3db60d0a4c4bb0c83b85 59ff0f653c8d6ae135f8f78580fec64a 94b…
28632 srsra v6.2s, v27.2s, #1 ff1b6b175be2d3df52df845d98f4f55d 3c9c985cf83f673c77f273019b6e1e7b 0000…
[all …]
/external/vixl/test/test-trace-reference/
Dlog-disasm1510 0x~~~~~~~~~~~~~~~~ 5f4137d5 srsra d21, d30, #63
1511 0x~~~~~~~~~~~~~~~~ 4f0a37db srsra v27.16b, v30.16b, #6
1512 0x~~~~~~~~~~~~~~~~ 4f653594 srsra v20.2d, v12.2d, #27
1513 0x~~~~~~~~~~~~~~~~ 0f3b3620 srsra v0.2s, v17.2s, #5
1514 0x~~~~~~~~~~~~~~~~ 0f11360e srsra v14.4h, v16.4h, #15
1515 0x~~~~~~~~~~~~~~~~ 4f2c3472 srsra v18.4s, v3.4s, #20
1516 0x~~~~~~~~~~~~~~~~ 0f0f3435 srsra v21.8b, v1.8b, #1
1517 0x~~~~~~~~~~~~~~~~ 4f1e373f srsra v31.8h, v25.8h, #2
Dlog-disasm-colour1510 0x~~~~~~~~~~~~~~~~ 5f4137d5 srsra d21, d30, #63
1511 0x~~~~~~~~~~~~~~~~ 4f0a37db srsra v27.16b, v30.16b, #6
1512 0x~~~~~~~~~~~~~~~~ 4f653594 srsra v20.2d, v12.2d, #27
1513 0x~~~~~~~~~~~~~~~~ 0f3b3620 srsra v0.2s, v17.2s, #5
1514 0x~~~~~~~~~~~~~~~~ 0f11360e srsra v14.4h, v16.4h, #15
1515 0x~~~~~~~~~~~~~~~~ 4f2c3472 srsra v18.4s, v3.4s, #20
1516 0x~~~~~~~~~~~~~~~~ 0f0f3435 srsra v21.8b, v1.8b, #1
1517 0x~~~~~~~~~~~~~~~~ 4f1e373f srsra v31.8h, v25.8h, #2
Dlog-all3843 0x~~~~~~~~~~~~~~~~ 5f4137d5 srsra d21, d30, #63
3845 0x~~~~~~~~~~~~~~~~ 4f0a37db srsra v27.16b, v30.16b, #6
3847 0x~~~~~~~~~~~~~~~~ 4f653594 srsra v20.2d, v12.2d, #27
3849 0x~~~~~~~~~~~~~~~~ 0f3b3620 srsra v0.2s, v17.2s, #5
3851 0x~~~~~~~~~~~~~~~~ 0f11360e srsra v14.4h, v16.4h, #15
3853 0x~~~~~~~~~~~~~~~~ 4f2c3472 srsra v18.4s, v3.4s, #20
3855 0x~~~~~~~~~~~~~~~~ 0f0f3435 srsra v21.8b, v1.8b, #1
3857 0x~~~~~~~~~~~~~~~~ 4f1e373f srsra v31.8h, v25.8h, #2
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1744 __ srsra(d21, d30, 63); in GenerateTestSequenceNEON() local
1745 __ srsra(v27.V16B(), v30.V16B(), 6); in GenerateTestSequenceNEON() local
1746 __ srsra(v20.V2D(), v12.V2D(), 27); in GenerateTestSequenceNEON() local
1747 __ srsra(v0.V2S(), v17.V2S(), 5); in GenerateTestSequenceNEON() local
1748 __ srsra(v14.V4H(), v16.V4H(), 15); in GenerateTestSequenceNEON() local
1749 __ srsra(v18.V4S(), v3.V4S(), 20); in GenerateTestSequenceNEON() local
1750 __ srsra(v21.V8B(), v1.V8B(), 1); in GenerateTestSequenceNEON() local
1751 __ srsra(v31.V8H(), v25.V8H(), 2); in GenerateTestSequenceNEON() local
Dtest-simulator-aarch64.cc4237 DEFINE_TEST_NEON_2OPIMM(srsra, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4272 DEFINE_TEST_NEON_2OPIMM_SCALAR_D(srsra, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc4894 srsra(vf, rd, rn, right_shift); in VisitNEONScalarShiftImmediate()
4997 srsra(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
Dsimulator-aarch64.h2592 LogicVRegister srsra(VectorFormat vform,
Dassembler-aarch64.h2266 void srsra(const VRegister& vd, const VRegister& vn, int shift);
Dmacro-assembler-aarch64.h2460 V(srsra, Srsra) \
Dlogic-aarch64.cc1831 LogicVRegister Simulator::srsra(VectorFormat vform, in srsra() function in vixl::aarch64::Simulator
Dassembler-aarch64.cc3743 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) { in srsra() function in vixl::aarch64::Assembler
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3380 void srsra(const VRegister& vd, const VRegister& vn, int shift)
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4728 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4780 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
/external/swiftshader/third_party/LLVM/test/MC/ELF/
Dmany-section.s45402 .section srsra