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/external/libjpeg-turbo/simd/
DMakefile.am7 jccolext-sse2.asm jcgryext-sse2.asm jdcolext-sse2.asm jdmrgext-sse2.asm \
8 jccolext-sse2-64.asm jcgryext-sse2-64.asm jdcolext-sse2-64.asm \
9 jdmrgext-sse2-64.asm jccolext-altivec.c jcgryext-altivec.c \
16 jccolor-sse2-64.asm jcgray-sse2-64.asm jchuff-sse2-64.asm \
17 jcsample-sse2-64.asm jdcolor-sse2-64.asm jdmerge-sse2-64.asm \
18 jdsample-sse2-64.asm jfdctfst-sse2-64.asm jfdctint-sse2-64.asm \
19 jidctflt-sse2-64.asm jidctfst-sse2-64.asm jidctint-sse2-64.asm \
20 jidctred-sse2-64.asm jquantf-sse2-64.asm jquanti-sse2-64.asm
22 jccolor-sse2-64.lo: jccolext-sse2-64.asm
23 jcgray-sse2-64.lo: jcgryext-sse2-64.asm
[all …]
DCMakeLists.txt25 set(SIMD_BASENAMES jfdctflt-sse-64 jccolor-sse2-64 jcgray-sse2-64
26 jchuff-sse2-64 jcsample-sse2-64 jdcolor-sse2-64 jdmerge-sse2-64
27 jdsample-sse2-64 jfdctfst-sse2-64 jfdctint-sse2-64 jidctflt-sse2-64
28 jidctfst-sse2-64 jidctint-sse2-64 jidctred-sse2-64 jquantf-sse2-64
29 jquanti-sse2-64)
35 jidctflt-sse jquant-sse jccolor-sse2 jcgray-sse2 jchuff-sse2 jcsample-sse2
36 jdcolor-sse2 jdmerge-sse2 jdsample-sse2 jfdctfst-sse2 jfdctint-sse2
37 jidctflt-sse2 jidctfst-sse2 jidctint-sse2 jidctred-sse2 jquantf-sse2
38 jquanti-sse2)
DMakefile.in115 jquant-sse.asm jccolor-sse2.asm jcgray-sse2.asm \
116 jchuff-sse2.asm jcsample-sse2.asm jdcolor-sse2.asm \
117 jdmerge-sse2.asm jdsample-sse2.asm jfdctfst-sse2.asm \
118 jfdctint-sse2.asm jidctflt-sse2.asm jidctfst-sse2.asm \
119 jidctint-sse2.asm jidctred-sse2.asm jquantf-sse2.asm \
120 jquanti-sse2.asm jsimd_mips.c jsimd_mips_dspr2_asm.h \
122 jsimd_x86_64.c jfdctflt-sse-64.asm jccolor-sse2-64.asm \
123 jcgray-sse2-64.asm jchuff-sse2-64.asm jcsample-sse2-64.asm \
124 jdcolor-sse2-64.asm jdmerge-sse2-64.asm jdsample-sse2-64.asm \
125 jfdctfst-sse2-64.asm jfdctint-sse2-64.asm jidctflt-sse2-64.asm \
[all …]
/external/libjpeg-turbo/
DAndroid.bp91 "simd/jccolor-sse2.asm",
93 "simd/jcgray-sse2.asm",
94 "simd/jchuff-sse2.asm",
96 "simd/jcsample-sse2.asm",
98 "simd/jdcolor-sse2.asm",
100 "simd/jdmerge-sse2.asm",
102 "simd/jdsample-sse2.asm",
106 "simd/jfdctfst-sse2.asm",
108 "simd/jfdctint-sse2.asm",
110 "simd/jidctflt-sse2.asm",
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dvec_shuffle-16.ll1 ; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefi…
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2
5 ; sse2: t1:
8 ; sse2: pshufd
9 ; sse2-NEXT: ret
15 ; sse2: t2:
18 ; sse2: pshufd
19 ; sse2-NEXT: ret
25 ; sse2: t3:
28 ; sse2: pshufd
[all …]
Dpic-load-remat.ll1 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb
8 …%tmp4403 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> zeroinitializer, <8 x i16> zeroin…
9 …%tmp4443 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> zeroinitializer, <8 x i16> zeroin…
10 …%tmp4609 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast…
12 …%tmp4658 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x …
13 …%tmp4669 = tail call <8 x i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -231…
14 …%tmp4679 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4669, <8 x i16> %tmp4669 ) no…
16 …%tmp4700 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4689, <8 x i16> zeroinitializ…
19 …%tmp4779 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4772, <8 x i16> bitcast (<4 x …
21 …%tmp4821 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4810, <8 x i16> zeroinitializ…
[all …]
Dvec_shift3.ll1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllq
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw
3 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 2
7 …%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 %bits ) nounwind readnone …
13 …%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 10 ) nounwind readnone ; …
20 …%tmp4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w( <8 x i16> %tmp2, i32 %bits ) nounwind readnone…
25 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
26 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
Dvec_shift.ll1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllw
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psrlq
3 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw
9 …%tmp9 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp8, <8 x i16> %tmp6 ) nounwind rea…
19 …%tmp9 = tail call <8 x i16> @llvm.x86.sse2.psra.w( <8 x i16> %tmp2, <8 x i16> %tmp8 ) ; <<8 x i16…
24 declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
28 …%tmp9 = tail call <2 x i64> @llvm.x86.sse2.psrl.q( <2 x i64> %b1, <2 x i64> %c ) nounwind readnone…
32 declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
34 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
Davx-intrinsics-x86.ll53 …%res = call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>…
56 declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind readnone
61 …%res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x d…
64 declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone
69 …%res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x d…
72 declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
79 %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
82 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
89 %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
92 declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readnone
[all …]
D2007-05-17-ShuffleISelBug.ll1 ; RUN: llc < %s -march=x86 -mattr=+sse2
2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep punpckhwd
4 declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>)
6 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>)
15 …%tmp838 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp832, <8 x i16> < i16 8, i16 und…
16 …%tmp1020 = tail call <16 x i8> @llvm.x86.sse2.packuswb.128( <8 x i16> zeroinitializer, <8 x i16> %…
/external/llvm/test/CodeGen/X86/
Dsse2-intrinsics-x86.ll2 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse2 | FileCheck %s --check-prefix=SSE
15 …%res = call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>…
18 declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind readnone
31 …%res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x d…
34 declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone
47 …%res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x d…
50 declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
71 %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
74 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
91 %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
[all …]
Dsse2-intrinsics-x86-upgrade.ll2 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
9 %res = call <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
12 declare <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64>, i32) nounwind readnone
20 %res = call <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
23 declare <2 x i64> @llvm.x86.sse2.psrl.dq.bs(<2 x i64>, i32) nounwind readnone
30 %res = call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
33 declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone
41 %res = call <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64> %a0, i32 8) ; <<2 x i64>> [#uses=1]
44 declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32) nounwind readnone
52 %res = call <2 x double> @llvm.x86.sse2.cvtdq2pd(<4 x i32> %a0) ; <<2 x double>> [#uses=1]
[all …]
Dpic-load-remat.ll1 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb
8 …%tmp4403 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> zeroinitializer, <8 x i16> zeroin…
9 …%tmp4443 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> zeroinitializer, <8 x i16> zeroin…
10 …%tmp4609 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast…
12 …%tmp4658 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x …
13 …%tmp4669 = tail call <8 x i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -231…
14 …%tmp4679 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4669, <8 x i16> %tmp4669 ) no…
16 …%tmp4700 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4689, <8 x i16> zeroinitializ…
19 …%tmp4779 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4772, <8 x i16> bitcast (<4 x …
21 …%tmp4821 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4810, <8 x i16> zeroinitializ…
[all …]
Dvec_shift5.ll2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
19 …%1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> <i16 1, i16 2, i16 4, i16 8, i16 1, i16 …
33 …%1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i1…
47 …%1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> <i16 4, i16 8, i16 16, i16 32, i16 4, i1…
61 %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> <i32 1, i32 2, i32 4, i32 8>, i32 3)
75 %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
89 %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> <i32 4, i32 8, i32 16, i32 32>, i32 3)
104 %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> <i64 1, i64 2>, i32 3)
119 %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> <i64 8, i64 16>, i32 3)
[all …]
Dvec_shift.ll2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
18 …%tmp9 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp8, <8 x i16> %tmp6 ) nounwind rea…
39 …%tmp9 = tail call <8 x i16> @llvm.x86.sse2.psra.w( <8 x i16> %tmp2, <8 x i16> %tmp8 ) ; <<8 x i16…
44 declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
57 …%tmp9 = tail call <2 x i64> @llvm.x86.sse2.psrl.q( <2 x i64> %b1, <2 x i64> %c ) nounwind readnone…
61 declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
63 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
Dvec_shift3.ll2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
18 …%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 %bits ) nounwind readnone …
33 …%tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 10 ) nounwind readnone ; …
51 …%tmp4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w( <8 x i16> %tmp2, i32 %bits ) nounwind readnone…
56 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
57 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
/external/libvpx/libvpx/vpx_dsp/x86/
Dhighbd_variance_sse2.c260 DECLS(sse2);
276 unsigned int sse2; \
279 &sse2, NULL, NULL); \
281 sse += sse2; \
285 &sse2, NULL, NULL); \
287 sse += sse2; \
290 &sse2, NULL, NULL); \
292 sse += sse2; \
310 uint32_t sse2; \
313 &sse2, NULL, NULL); \
[all …]
Dvpx_asm_stubs.c62 FUN_CONV_1D(horiz, x0_q4, x_step_q4, h, src, , sse2);
63 FUN_CONV_1D(vert, y0_q4, y_step_q4, v, src - src_stride * 3, , sse2);
64 FUN_CONV_1D(avg_horiz, x0_q4, x_step_q4, h, src, avg_, sse2);
65 FUN_CONV_1D(avg_vert, y0_q4, y_step_q4, v, src - src_stride * 3, avg_, sse2);
77 FUN_CONV_2D(, sse2);
78 FUN_CONV_2D(avg_, sse2);
143 HIGH_FUN_CONV_1D(horiz, x0_q4, x_step_q4, h, src, , sse2);
144 HIGH_FUN_CONV_1D(vert, y0_q4, y_step_q4, v, src - src_stride * 3, , sse2);
145 HIGH_FUN_CONV_1D(avg_horiz, x0_q4, x_step_q4, h, src, avg_, sse2);
147 sse2);
[all …]
Dvariance_sse2.c322 DECLS(sse2, sse2);
336 unsigned int sse2; \
339 &sse2, NULL, NULL); \
341 sse += sse2; \
345 &sse2, NULL, NULL); \
347 sse += sse2; \
350 &sse2, NULL, NULL); \
352 sse += sse2; \
374 FNS(sse2, sse2);
392 DECLS(sse2, sse2);
[all …]
/external/llvm/test/Transforms/InstCombine/
Dx86-sse2.ll8 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> [[TMP1]])
14 %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
25 %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
32 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a, <2 x …
36 %2 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a, <2 x double> %1)
49 %5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4)
62 %5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4)
69 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a, <2 x …
73 %2 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a, <2 x double> %1)
86 %5 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %2, <2 x double> %4)
[all …]
/external/swiftshader/third_party/LLVM/test/Assembler/
DAutoUpgradeIntrinsics.ll6 declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readnone
7 declare <2 x double> @llvm.x86.sse2.loadu.pd(double*) nounwind readnone
10 %v1 = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a)
11 %v2 = call <2 x double> @llvm.x86.sse2.loadu.pd(double* %b)
20 declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x double>) nounwind readnone
21 declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind readnone
22 declare void @llvm.x86.sse2.movnt.i(i8*, i32) nounwind readnone
28 call void @llvm.x86.sse2.movnt.dq(i8* %B, <2 x double> %C)
30 call void @llvm.x86.sse2.movnt.pd(i8* %B, <2 x double> %C)
32 call void @llvm.x86.sse2.movnt.i(i8* %B, i32 %D)
/external/skqp/src/jumper/
Dbuild_stages.py37 sse2 = ['-msse2', '-mno-sse3', '-mno-ssse3', '-mno-sse4.1'] variable
38 subprocess.check_call(clang + cflags + sse2 +
41 subprocess.check_call(clang + cflags + sse2 + win +
44 subprocess.check_call(clang + cflags + sse2 + x86 +
47 subprocess.check_call(clang + cflags + sse2 + win + x86 +
51 subprocess.check_call(clang + cflags + sse2 +
54 subprocess.check_call(clang + cflags + sse2 + win +
57 subprocess.check_call(clang + cflags + sse2 + x86 +
60 subprocess.check_call(clang + cflags + sse2 + win + x86 +
/external/skia/src/jumper/
Dbuild_stages.py37 sse2 = ['-msse2', '-mno-sse3', '-mno-ssse3', '-mno-sse4.1'] variable
38 subprocess.check_call(clang + cflags + sse2 +
41 subprocess.check_call(clang + cflags + sse2 + win +
44 subprocess.check_call(clang + cflags + sse2 + x86 +
47 subprocess.check_call(clang + cflags + sse2 + win + x86 +
51 subprocess.check_call(clang + cflags + sse2 +
54 subprocess.check_call(clang + cflags + sse2 + win +
57 subprocess.check_call(clang + cflags + sse2 + x86 +
60 subprocess.check_call(clang + cflags + sse2 + win + x86 +
/external/swiftshader/third_party/LLVM/test/Transforms/ConstProp/
Dcalls.ll39 %i4 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> <double 1.75, double undef>) nounwind
40 %i5 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> <double 1.75, double undef>) nounwind
41 %i6 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> <double 1.75, double undef>) nounwind
42 %i7 = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> <double 1.75, double undef>) nounwind
58 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
59 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone
60 declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
61 declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
/external/valgrind/memcheck/tests/amd64/
Dxor-undef-amd64.stdout.exp14 Complain sse2 pxor
16 No complain sse2 pxor
18 Complain sse2 xorpd
20 No complain sse2 xorpd

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