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Searched refs:stencil_level (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_surface.c170 surf_level_winsys_to_drm(&surf_drm->stencil_level[i], in surf_winsys_to_drm()
171 &surf_ws->stencil_level[i], in surf_winsys_to_drm()
212 surf_level_drm_to_winsys(&surf_ws->stencil_level[i], in surf_drm_to_winsys()
213 &surf_drm->stencil_level[i], in surf_drm_to_winsys()
/external/libdrm/radeon/
Dradeon_surface.c798 struct radeon_surface_level *stencil_level = in eg_surface_init_1d_miptrees() local
799 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; in eg_surface_init_1d_miptrees()
806 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1, in eg_surface_init_1d_miptrees()
808 surf->stencil_offset = stencil_level[0].offset; in eg_surface_init_1d_miptrees()
820 struct radeon_surface_level *stencil_level = in eg_surface_init_2d_miptrees() local
821 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; in eg_surface_init_2d_miptrees()
829 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1, in eg_surface_init_2d_miptrees()
831 surf->stencil_offset = stencil_level[0].offset; in eg_surface_init_2d_miptrees()
1614 …r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0… in si_surface_init_1d_miptrees()
1615 surf->stencil_offset = surf->stencil_level[0].offset; in si_surface_init_1d_miptrees()
[all …]
Dradeon_surface.h137 struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL]; member
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c187 AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x; in radv_compute_level()
202 surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level]; in radv_compute_level()
500 if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x) in radv_amdgpu_winsys_surface_init()
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c175 AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x; in compute_level()
191 surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level]; in compute_level()
543 if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x) in amdgpu_surface_init()
/external/mesa3d/src/amd/vulkan/
Dradv_radeon_winsys.h202 struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL]; member
Dradv_image.c818 …is_stencil ? &image->surface.stencil_level[range->baseMipLevel] : &image->surface.level[range->bas… in radv_image_view_init()
Dradv_device.c1762 s_offs += iview->image->surface.stencil_level[level].offset; in radv_initialise_ds_surface()
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_winsys.h342 struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; member
Dr600_texture.c971 i, rtex->surface.stencil_level[i].offset, in r600_print_texture_info()
972 rtex->surface.stencil_level[i].slice_size, in r600_print_texture_info()
976 rtex->surface.stencil_level[i].nblk_x, in r600_print_texture_info()
977 rtex->surface.stencil_level[i].nblk_y, in r600_print_texture_info()
978 rtex->surface.stencil_level[i].mode, in r600_print_texture_info()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state.c2218 s_offs += rtex->surface.stencil_level[level].offset; in si_init_depth_surface()
3145 surflevel = tmp->surface.stencil_level; in si_create_sampler_view_custom()
/external/mesa3d/src/gallium/drivers/r600/
Devergreen_state.c718 surflevel = tmp->surface.stencil_level; in evergreen_create_sampler_view_custom()
1230 stencil_offset = rtex->surface.stencil_level[level].offset; in evergreen_init_depth_surface()