| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 258 uint32_t tiling_flags = 0; in radv_amdgpu_winsys_bo_set_metadata() local
261 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_set_metadata()
263 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */ in radv_amdgpu_winsys_bo_set_metadata()
265 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */ in radv_amdgpu_winsys_bo_set_metadata()
267 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->pipe_config); in radv_amdgpu_winsys_bo_set_metadata()
268 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw)); in radv_amdgpu_winsys_bo_set_metadata()
269 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh)); in radv_amdgpu_winsys_bo_set_metadata()
271 tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->tile_split)); in radv_amdgpu_winsys_bo_set_metadata()
272 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea)); in radv_amdgpu_winsys_bo_set_metadata()
273 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->num_banks)-1); in radv_amdgpu_winsys_bo_set_metadata()
[all …]
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_bo.c | 600 uint32_t tiling_flags; in amdgpu_buffer_get_metadata() local
609 tiling_flags = info.metadata.tiling_info; in amdgpu_buffer_get_metadata()
614 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */ in amdgpu_buffer_get_metadata()
616 else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */ in amdgpu_buffer_get_metadata()
619 md->pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in amdgpu_buffer_get_metadata()
620 md->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_buffer_get_metadata()
621 md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in amdgpu_buffer_get_metadata()
622 md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); in amdgpu_buffer_get_metadata()
623 md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in amdgpu_buffer_get_metadata()
624 md->num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in amdgpu_buffer_get_metadata()
[all …]
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| /external/libdrm/radeon/ |
| D | radeon_bo.c | 101 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling() argument
104 return boi->bom->funcs->bo_set_tiling(boi, tiling_flags, pitch); in radeon_bo_set_tiling()
109 uint32_t *tiling_flags, uint32_t *pitch) in radeon_bo_get_tiling() argument
112 return boi->bom->funcs->bo_get_tiling(boi, tiling_flags, pitch); in radeon_bo_get_tiling()
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| D | radeon_bo_gem.c | 235 static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags, in bo_set_tiling() argument
242 args.tiling_flags = tiling_flags; in bo_set_tiling()
252 static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags, in bo_get_tiling() argument
268 *tiling_flags = args.tiling_flags; in bo_get_tiling()
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| D | radeon_bo.h | 68 int radeon_bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch);
69 int radeon_bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch);
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| D | radeon_bo_int.h | 37 int (*bo_set_tiling)(struct radeon_bo_int *bo, uint32_t tiling_flags,
39 int (*bo_get_tiling)(struct radeon_bo_int *bo, uint32_t *tiling_flags,
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_bo.c | 877 if (args.tiling_flags & RADEON_TILING_MICRO) in radeon_bo_get_metadata()
879 else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE) in radeon_bo_get_metadata()
882 if (args.tiling_flags & RADEON_TILING_MACRO) in radeon_bo_get_metadata()
885 md->bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_get_metadata()
886 md->bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_get_metadata()
887 …md->tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_… in radeon_bo_get_metadata()
888 …md->mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MA… in radeon_bo_get_metadata()
890 md->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT); in radeon_bo_get_metadata()
906 args.tiling_flags |= RADEON_TILING_MICRO; in radeon_bo_set_metadata()
908 args.tiling_flags |= RADEON_TILING_MICRO_SQUARE; in radeon_bo_set_metadata()
[all …]
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| /external/mesa3d/src/intel/isl/tests/ |
| D | isl_surf_get_image_offset_test.c | 145 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0()
193 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0()
254 .tiling_flags = ISL_TILING_Y0_BIT); in test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0()
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| /external/mesa3d/src/intel/isl/ |
| D | isl.c | 256 isl_tiling_flags_t tiling_flags = info->tiling_flags; in isl_surf_choose_tiling() local
261 assert(tiling_flags == ISL_TILING_HIZ_BIT); in isl_surf_choose_tiling()
269 assert(tiling_flags == ISL_TILING_CCS_BIT); in isl_surf_choose_tiling()
275 isl_gen6_filter_tiling(dev, info, &tiling_flags); in isl_surf_choose_tiling()
278 isl_gen6_filter_tiling(dev, info, &tiling_flags); in isl_surf_choose_tiling()
283 if (tiling_flags & (1u << (__tiling))) { \ in isl_surf_choose_tiling()
1404 .tiling_flags = ISL_TILING_HIZ_BIT); in isl_surf_get_hiz_surf()
1440 .tiling_flags = ISL_TILING_Y0_BIT); in isl_surf_get_mcs_surf()
1504 .tiling_flags = ISL_TILING_CCS_BIT); in isl_surf_get_ccs_surf()
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| D | isl.h | 819 isl_tiling_flags_t tiling_flags; member
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_common_context.c | 512 uint32_t tiling_flags = 0, pitch = 0; in radeon_update_renderbuffers() local
528 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch); in radeon_update_renderbuffers()
537 if (tiling_flags & RADEON_TILING_MACRO) in radeon_update_renderbuffers()
539 if (tiling_flags & RADEON_TILING_MICRO) in radeon_update_renderbuffers()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_common_context.c | 512 uint32_t tiling_flags = 0, pitch = 0; in radeon_update_renderbuffers() local
528 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch); in radeon_update_renderbuffers()
537 if (tiling_flags & RADEON_TILING_MACRO) in radeon_update_renderbuffers()
539 if (tiling_flags & RADEON_TILING_MICRO) in radeon_update_renderbuffers()
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| /external/mesa3d/src/intel/vulkan/ |
| D | anv_image.c | 141 isl_tiling_flags_t tiling_flags = in make_surface() local
146 tiling_flags &= anv_info->isl_tiling_flags; in make_surface()
148 assert(tiling_flags); in make_surface()
171 .tiling_flags = tiling_flags); in make_surface()
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| D | anv_blorp.c | 165 .tiling_flags = ISL_TILING_LINEAR_BIT); in get_blorp_surf_for_anv_buffer()
559 .tiling_flags = ISL_TILING_LINEAR_BIT); in do_buffer_copy()
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| /external/kernel-headers/original/uapi/drm/ |
| D | radeon_drm.h | 858 __u32 tiling_flags; member
864 __u32 tiling_flags; member
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| /external/libdrm/include/drm/ |
| D | radeon_drm.h | 859 uint32_t tiling_flags; member
865 uint32_t tiling_flags; member
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| /external/mesa3d/src/intel/blorp/ |
| D | blorp_blit.c | 1423 .tiling_flags = 1 << info->surf.tiling, in surf_convert_to_single_slice()
|