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/external/clang/test/CodeGen/
Dbuiltins-hexagon.c5 int v16 __attribute__((__vector_size__(64))); in foo() local
1759 __builtin_HEXAGON_V6_extractw(v16, 0); in foo()
1777 __builtin_HEXAGON_V6_pred_and_n(v16, v16); in foo()
1779 __builtin_HEXAGON_V6_pred_and(v16, v16); in foo()
1783 __builtin_HEXAGON_V6_pred_not(v16); in foo()
1789 __builtin_HEXAGON_V6_pred_or_n(v16, v16); in foo()
1791 __builtin_HEXAGON_V6_pred_or(v16, v16); in foo()
1799 __builtin_HEXAGON_V6_pred_xor(v16, v16); in foo()
1803 __builtin_HEXAGON_V6_vabsdiffh(v16, v16); in foo()
1807 __builtin_HEXAGON_V6_vabsdiffub(v16, v16); in foo()
[all …]
/external/libhevc/common/arm64/
Dihevc_intra_pred_chroma_dc.s193 dup v16.8b,w11
206 st2 {v16.8b, v17.8b}, [x2],#16
209 st2 {v16.8b, v17.8b}, [x5],#16
210 st2 {v16.8b, v17.8b}, [x8],#16
213 st2 {v16.8b, v17.8b}, [x10],#16
216 st2 {v16.8b, v17.8b}, [x2], x6
217 st2 {v16.8b, v17.8b}, [x5], x6
218 st2 {v16.8b, v17.8b}, [x8], x6
219 st2 {v16.8b, v17.8b}, [x10], x6
222 st2 {v16.8b, v17.8b}, [x2],#16
[all …]
Dihevc_deblk_luma_vert.s103 movi v16.8h, #0x2
234 mla v20.8h, v0.8h, v16.8h
286 mla v26.8h, v0.8h, v16.8h
295 umin v16.8b, v26.8b , v30.8b
299 umax v26.8b, v16.8b , v31.8b
420 uaddw v16.8h, v0.8h , v6.8b
422 rshrn v2.8b,v16.8h,#2
425 umin v16.8b, v2.8b , v27.8b
430 umax v5.8b, v16.8b , v28.8b
462 movi v16.8h, #0x3
[all …]
Dihevc_intra_pred_luma_dc.s203 dup v16.8b, v18.b[0] //dc_val
263 bsl v20.8b, v3.8b , v16.8b //row 1 (prol)
272 bsl v21.8b, v3.8b , v16.8b //row 2 (prol)
280 bsl v20.8b, v3.8b , v16.8b //row 3 (prol)
288 bsl v21.8b, v3.8b , v16.8b //row 4 (prol)
296 bsl v20.8b, v3.8b , v16.8b //row 5 (prol)
305 bsl v21.8b, v3.8b , v16.8b //row 6 (prol)
314 bsl v20.8b, v3.8b , v16.8b //row 7 (prol)
333 st1 {v16.8b},[x2], x3
334 st1 {v16.8b},[x2], x3
[all …]
Dihevc_intra_pred_luma_vert.s185 …ld1 {v16.8b, v17.8b}, [x6] //ld for repl to cols src[2nt+1+col(0:15)] (0 ignored for …
223 bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
224 bsl v3.8b, v25.8b , v16.8b
239 bsl v1.8b, v24.8b , v16.8b
240 bsl v6.8b, v25.8b , v16.8b
264 bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
265 bsl v3.8b, v25.8b , v16.8b
277 bsl v1.8b, v24.8b , v16.8b
278 bsl v6.8b, v25.8b , v16.8b
294 bsl v18.8b, v24.8b , v16.8b //only select row values from q12(predpixel)
[all …]
Dihevc_weighted_pred_uni.s196 smull v16.4s, v5.4h, v0.h[0] //vmull_n_s16(pi2_src_val2, (int16_t) wgt0) iv iteration
203 add v16.4s, v16.4s , v30.4s //vaddq_s32(i4_tmp2_t, tmp_lvl_shift_t) iv iteration
208 sshl v16.4s,v16.4s,v28.4s
217 sqxtun v16.4h, v16.4s //vqmovun_s32(sto_res_tmp1) iv iteration
221 uqxtn v16.8b, v16.8h //vqmovn_u16(sto_res_tmp3) iv iteration
224 st1 {v16.s}[0],[x6],x3 //store pu1_dst iv iteration
/external/capstone/suite/MC/AArch64/
Dneon-simd-ldst-multi-elem.s.cs11 0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15]
15 0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15]
19 0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15]
23 0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15]
27 0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15]
31 0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15]
35 0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15]
39 0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15]
43 0xef,0x25,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
47 0xef,0x25,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
[all …]
Dneon-simd-post-ldst-multi-elem.s.cs11 0xef,0xa5,0xc2,0x4c = ld1 {v15.8h, v16.8h}, [x15], x2
15 0xef,0xa5,0xc3,0x0c = ld1 {v15.4h, v16.4h}, [x15], x3
19 0xef,0x65,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2
23 0xef,0x65,0xc3,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3
27 0xef,0x25,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
31 0xef,0x25,0xc4,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
35 0xef,0x85,0xc2,0x4c = ld2 {v15.8h, v16.8h}, [x15], x2
39 0xef,0x85,0xc3,0x0c = ld2 {v15.4h, v16.4h}, [x15], x3
42 0xef,0x45,0xc2,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2
46 0xef,0x45,0xc3,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3
[all …]
Dneon-simd-ldst-one-elem.s.cs11 0xef,0xc5,0x60,0x4d = ld2r {v15.8h, v16.8h}, [x15]
15 0xef,0xc5,0x60,0x0d = ld2r {v15.4h, v16.4h}, [x15]
19 0xef,0xe5,0x40,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15]
23 0xef,0xe5,0x40,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15]
27 0xef,0xe5,0x60,0x4d = ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
31 0xef,0xe5,0x60,0x0d = ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
39 0xef,0x59,0x60,0x4d = ld2 {v15.h, v16.h}[7], [x15]
43 0xef,0x79,0x40,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15]
47 0xef,0x79,0x60,0x4d = ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15]
55 0xef,0x59,0x20,0x4d = st2 {v15.h, v16.h}[7], [x15]
[all …]
Dneon-compare-instructions.s.cs4 0x0f,0x8e,0x71,0x2e = cmeq v15.4h, v16.4h, v17.4h
11 0x0f,0x3e,0x71,0x2e = cmhs v15.4h, v16.4h, v17.4h
18 0x0f,0x3e,0x71,0x2e = cmhs v15.4h, v16.4h, v17.4h
25 0x0f,0x3e,0x71,0x0e = cmge v15.4h, v16.4h, v17.4h
32 0x0f,0x3e,0x71,0x0e = cmge v15.4h, v16.4h, v17.4h
39 0x0f,0x36,0x71,0x2e = cmhi v15.4h, v16.4h, v17.4h
46 0x0f,0x36,0x71,0x2e = cmhi v15.4h, v16.4h, v17.4h
53 0x0f,0x36,0x71,0x0e = cmgt v15.4h, v16.4h, v17.4h
60 0x0f,0x36,0x71,0x0e = cmgt v15.4h, v16.4h, v17.4h
67 0x0f,0x8e,0x71,0x0e = cmtst v15.4h, v16.4h, v17.4h
[all …]
/external/libhevc/decoder/arm64/
Dihevcd_fmt_conv_420sp_to_rgba8888.s227 UADDW v16.8h, v7.8h , v30.8b ////Q8 - HAS Y + R
236 sqxtun v16.8b, v16.8h
247 ZIP1 v27.8b, v16.8b, v17.8b
248 ZIP2 v17.8b, v16.8b, v17.8b
249 mov v16.d[0], v27.d[0]
260 mov v16.d[1], v17.d[0]
263 ZIP1 v27.8h, v14.8h, v16.8h
264 ZIP2 v26.8h, v14.8h, v16.8h
272 ZIP1 v16.4s, v26.4s, v19.4s
277 ST1 {v16.4s},[x2],#16
[all …]
/external/llvm/test/MC/AArch64/
Dneon-simd-post-ldst-multi-elem.s38 ld1 { v15.8h, v16.8h }, [x15], x2
42 ld1 { v15.4h, v16.4h }, [x15], x3
67 ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2
71 ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3
96 ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2
100 ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4
125 ld2 { v15.8h, v16.8h }, [x15], x2
129 ld2 { v15.4h, v16.4h }, [x15], x3
151 ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
155 ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
[all …]
Dneon-simd-ldst-multi-elem.s29 st1 { v15.8h, v16.8h }, [x15]
33 st1 { v15.4h, v16.4h }, [x15]
46 st1 { v15.8h-v16.8h }, [x15]
50 st1 { v15.4h-v16.4h }, [x15]
66 st1 { v15.8h, v16.8h, v17.8h }, [x15]
70 st1 { v15.4h, v16.4h, v17.4h }, [x15]
103 st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
107 st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
140 st2 { v15.8h, v16.8h }, [x15]
144 st2 { v15.4h, v16.4h }, [x15]
[all …]
Dneon-simd-ldst-one-elem.s30 ld2r { v15.8h, v16.8h }, [x15]
34 ld2r { v15.4h, v16.4h }, [x15]
47 ld3r { v15.8h, v16.8h, v17.8h }, [x15]
51 ld3r { v15.4h, v16.4h, v17.4h }, [x15]
64 ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
68 ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
97 ld2 { v15.h, v16.h }[7], [x15]
106 ld3 { v15.h, v16.h, v17.h }[7], [x15]
115 ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]
140 st2 { v15.h, v16.h }[7], [x15]
[all …]
Dfullfp16-diagnostics.s4 fmla v0.4h, v1.4h, v16.h[3]
14 fmls v0.4h, v1.4h, v16.h[3]
24 fmul v0.4h, v1.4h, v16.h[3]
34 fmulx v0.4h, v1.4h, v16.h[3]
44 fmla h0, h1, v16.h[3]
54 fmls h0, h1, v16.h[3]
64 fmul h0, h1, v16.h[3]
74 fmulx h0, h1, v16.h[3]
Dneon-compare-instructions.s11 cmeq v15.4h, v16.4h, v17.4h
33 cmhs v15.4h, v16.4h, v17.4h
41 cmls v15.4h, v17.4h, v16.4h
70 cmge v15.4h, v16.4h, v17.4h
78 cmle v15.4h, v17.4h, v16.4h
107 cmhi v15.4h, v16.4h, v17.4h
115 cmlo v15.4h, v17.4h, v16.4h
144 cmgt v15.4h, v16.4h, v17.4h
152 cmlt v15.4h, v17.4h, v16.4h
179 cmtst v15.4h, v16.4h, v17.4h
[all …]
/external/boringssl/ios-aarch64/crypto/fipsmodule/
Dghashv8-armx64.S16 ext v16.16b,v18.16b,v19.16b,#8 //t0=0xc2....01
19 and v18.16b,v18.16b,v16.16b
22 and v16.16b,v16.16b,v17.16b
24 eor v20.16b,v3.16b,v16.16b //twisted H
28 ext v16.16b,v20.16b,v20.16b,#8 //Karatsuba pre-processing
30 eor v16.16b,v16.16b,v20.16b
32 pmull v1.1q,v16.1d,v16.1d
51 ext v21.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
124 ld1 {v16.2d},[x2],#16 //load [rotated] I[0]
127 rev64 v16.16b,v16.16b
[all …]
/external/boringssl/linux-aarch64/crypto/fipsmodule/
Dghashv8-armx64.S17 ext v16.16b,v18.16b,v19.16b,#8 //t0=0xc2....01
20 and v18.16b,v18.16b,v16.16b
23 and v16.16b,v16.16b,v17.16b
25 eor v20.16b,v3.16b,v16.16b //twisted H
29 ext v16.16b,v20.16b,v20.16b,#8 //Karatsuba pre-processing
31 eor v16.16b,v16.16b,v20.16b
33 pmull v1.1q,v16.1d,v16.1d
52 ext v21.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
125 ld1 {v16.2d},[x2],#16 //load [rotated] I[0]
128 rev64 v16.16b,v16.16b
[all …]
/external/libavc/common/armv8/
Dih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s107 ld1 {v16.2s}, [x0], x2 // Vector load from src[4_0]
126 uaddl v26.8h, v13.8b, v16.8b
203 uaddl v24.8h, v15.8b, v16.8b
282 uaddl v24.8h, v16.8b, v17.8b
368 uaddl v26.8h, v16.8b, v13.8b
444 mov v12.16b, v16.16b
450 mov v16.8b, v24.8b
468 uaddl v16.8h, v2.8b, v8.8b
474 mls v12.8h, v16.8h , v24.8h
476 uaddl v16.8h, v6.8b, v8.8b
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s168 ld1 {v16.2s}, [x0], x2 // Vector load from src[4_0]
188 uaddl v26.8h, v13.8b, v16.8b
271 uaddl v24.8h, v15.8b, v16.8b
355 uaddl v24.8h, v16.8b, v17.8b
446 uaddl v26.8h, v16.8b, v13.8b
527 mov v12.16b, v16.16b
535 mov v16.8b, v24.8b
553 uaddl v16.8h, v2.8b, v8.8b
559 mls v12.8h, v16.8h , v24.8h
561 uaddl v16.8h, v6.8b, v8.8b
[all …]
Dih264_weighted_bi_pred_av8.s206 ld1 {v16.8b}, [x0], x3 //load row 4 in source 1
216 uxtl v16.8h, v16.8b //converting row 4 in source 1 to 16-bit
220 mul v16.8h, v16.8h , v2.h[0] //weight 1 mult. for row 4
221 mla v16.8h, v18.8h , v2.h[2] //weight 2 mult. for row 4
226 srshl v16.8h, v16.8h , v0.8h //rounds off the weighted samples from row 4
230 saddw v16.8h, v16.8h , v3.8b //adding offset for row 4
233 sqxtun v16.8b, v16.8h //saturating row 4 to unsigned 8-bit
238 st1 {v16.8b}, [x2], x5 //store row 4 in destination
252 ld1 {v16.8b, v17.8b}, [x0], x3 //load row 4 in source 1
274 uxtl v22.8h, v16.8b //converting row 4L in source 1 to 16-bit
[all …]
Dih264_deblk_luma_av8.s116 ld1 {v16.s}[0], [x5] //D16[0] contains cliptab
119 tbl v14.8b, {v16.16b}, v12.8b //
122 dup v16.16b, w3 //Q8 contains beta
130 cmhs v24.16b, v24.16b, v16.16b
131 cmhs v26.16b, v26.16b, v16.16b
132 cmhi v20.16b, v16.16b , v28.16b //Q10=(Ap<Beta)
133 cmhi v22.16b, v16.16b , v30.16b //Q11=(Aq<Beta)
147 urhadd v16.16b, v6.16b , v0.16b //Q8 = ((p0+q0+1) >> 1)
148 mov v17.d[0], v16.d[1]
157 uaddl v10.8h, v16.8b, v10.8b //Q14,Q5 = p2 + (p0+q0+1)>>1
[all …]
Dih264_inter_pred_filters_luma_vert_av8.s141 uaddl v16.8h, v2.8b, v8.8b // temp2 = src[1_0] + src[4_0]
149 mls v14.8h, v16.8h , v24.8h // temp -= temp2 * 5
150 uaddl v16.8h, v2.8b, v0.8b
152 mla v16.8h, v12.8h , v22.8h
160 mls v16.8h, v18.8h , v24.8h
169 sqrshrun v30.8b, v16.8h, #5
171 uaddl v16.8h, v5.8b, v3.8b
173 mla v16.8h, v12.8h , v22.8h
182 mls v16.8h, v26.8h , v24.8h
191 sqrshrun v31.8b, v16.8h, #5
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_post_twiddle.s173 uMULL v16.4s, v4.4h, v8.4h
192 ushR v16.4s, v16.4s, #16
198 sMLAL v16.4s, v5.4h, v8.4h
208 ADD v22.4s, v22.4s , v16.4s
222 mov v16.16b, v20.16b
233 MOV v31.8b, v16.8b
234 UZP1 v16.4h, v31.4h, v17.4h
239 uMULL v6.4s, v16.4h, v10.4h
261 NEG v16.4s, v6.4s
266 ADD v16.4s, v22.4s , v16.4s
[all …]
/external/libmpeg2/common/armv8/
Dideint_spatial_filter_av8.s68 movi v16.8h, #0
109 uabal v16.8h, v0.8b, v3.8b
125 addp v16.8h, v16.8h, v16.8h
129 uaddlp v16.2s, v16.4h
134 mul v16.2s, v16.2s, v30.2s
147 smov x5, v16.s[0]
175 smov x5, v16.s[1]

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