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Searched refs:v16i16 (Results 1 – 25 of 48) sorted by relevance

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/external/clang/test/CodeGen/
Dppc64-vector.c8 typedef short v16i16 __attribute__((vector_size (32))); typedef
10 struct v16i16 { v16i16 x; }; argument
43 v16i16 test_v16i16(v16i16 x) in test_v16i16()
49 struct v16i16 test_struct_v16i16(struct v16i16 x) in test_struct_v16i16()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost()
194 { ISD::SHL, MVT::v16i16, 2 }, in getArithmeticInstrCost()
195 { ISD::SRL, MVT::v16i16, 4 }, in getArithmeticInstrCost()
196 { ISD::SRA, MVT::v16i16, 4 }, in getArithmeticInstrCost()
213 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
216 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
219 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. in getArithmeticInstrCost()
225 { ISD::SDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
340 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
362 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
403 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
445 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
520 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
536 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
555 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
667 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
421 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
426 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
430 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
431 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
432 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
433 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
434 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
[all …]
DX86RegisterInfo.td471 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
480 def VR256L : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
482 def VR256H : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
507 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
DX86ISelLowering.cpp934 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
942 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
950 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); in X86TargetLowering()
982 for (auto VT : { MVT::v32i8, MVT::v16i16 }) { in X86TargetLowering()
989 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); in X86TargetLowering()
999 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1002 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1005 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1011 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1018 for (auto VT : { MVT::v32i8, MVT::v16i16 }) in X86TargetLowering()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h62 v16i16 = 20, // 16 x i16 enumerator
198 case v16i16: return i16; in getVectorElementType()
220 case v16i16: return 16; in getVectorNumElements()
279 case v16i16: in getSizeInBits()
349 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
505 V == MVT::v16i16 || V == MVT::v8i32 || V == MVT::v4i64); in is256BitVector()
DValueTypes.td43 def v16i16 : ValueType<256, 20>; // 16 x i16 vector value
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h82 v16i16 = 34, // 16 x i16 enumerator
258 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
338 case v16i16: in getVectorElementType()
391 case v16i16: in getVectorNumElements()
491 case v16i16: in getSizeInBits()
618 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll18 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
46 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Davx512bw-mov.ll155 …%res = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i1…
158 declare <16 x i16> @llvm.masked.load.v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)
215 call void @llvm.masked.store.v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1>%mask)
218 declare void @llvm.masked.store.v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)
Davx-cmp.ll72 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
116 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Dvector-popcnt-256.ll140 %out = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %in)
203 …%out = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536,…
218 declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>)
Dbswap-vector.ll115 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
158 %r = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
329 %bs1 = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
330 %bs2 = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %bs1)
445 …%r = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> <i16 0, i16 1, i16 -1, i16 2, i16 -3, i16 4, i1…
Dvector-lzcnt-256.ll374 %out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %in, i1 0)
441 %out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %in, i1 -1)
684 …%out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536, …
703 …%out = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> <i16 256, i16 -1, i16 0, i16 255, i16 -65536, …
747 declare <16 x i16> @llvm.ctlz.v16i16(<16 x i16>, i1)
/external/llvm/test/Analysis/CostModel/X86/
Dctbits-cost.ll17 declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>)
70 %ctpop = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %a)
101 declare <16 x i16> @llvm.ctlz.v16i16(<16 x i16>, i1)
199 %ctlz = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %a, i1 0)
208 %ctlz = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %a, i1 1)
257 declare <16 x i16> @llvm.cttz.v16i16(<16 x i16>, i1)
355 %cttz = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %a, i1 0)
364 %cttz = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %a, i1 1)
Dbswap.ll16 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
80 %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
Dbitreverse.ll68 declare <16 x i16> @llvm.bitreverse.v16i16(<16 x i16>)
133 %bitreverse = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %a)
/external/swiftshader/third_party/LLVM/lib/VMCore/
DValueTypes.cpp128 case MVT::v16i16: return "v16i16"; in getEVTString()
175 case MVT::v16i16: return VectorType::get(Type::getInt16Ty(Context), 16); in getTypeForEVT()
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Davx-cmp.ll72 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
116 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CallingConv.td46 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
162 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
178 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
277 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
285 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86GenCallingConv.inc238 LocVT == MVT::v16i16 ||
267 LocVT == MVT::v16i16 ||
558 LocVT == MVT::v16i16 ||
603 LocVT == MVT::v16i16 ||
863 LocVT == MVT::v16i16 ||
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp148 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
149 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
175 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
176 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp209 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
210 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
446 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
/external/llvm/lib/IR/
DValueTypes.cpp166 case MVT::v16i16: return "v16i16"; in getEVTString()
244 case MVT::v16i16: return VectorType::get(Type::getInt16Ty(Context), 16); in getTypeForEVT()

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