Home
last modified time | relevance | path

Searched refs:v16i8 (Results 1 – 25 of 324) sorted by relevance

12345678910>>...13

/external/libyuv/files/source/
Drow_msa.cc78 v16i8 zero_m = {0}; \
80 vec0_m = (v8i16)__msa_ilvr_b((v16i8)in_y, (v16i8)in_y); \
81 vec1_m = (v8i16)__msa_ilvr_b((v16i8)zero_m, (v16i8)in_uv); \
128 vec0_m = (v8i16)__msa_ilvev_b((v16i8)in1, (v16i8)in0); \
129 vec1_m = (v8i16)__msa_ilvev_b((v16i8)in3, (v16i8)in2); \
154 y_out = (v16u8)__msa_pckev_b((v16i8)reg1_m, (v16i8)reg0_m); \
166 src0_m = (v16u8)__msa_ld_b((v16i8*)s, 0); \
167 src1_m = (v16u8)__msa_ld_b((v16i8*)s, 16); \
168 src2_m = (v16u8)__msa_ld_b((v16i8*)s, 32); \
169 src3_m = (v16u8)__msa_ld_b((v16i8*)s, 48); \
[all …]
Dscale_msa.cc33 src0 = (v16u8)__msa_ld_b((v16i8*)src_argb, 0); in ScaleARGBRowDown2_MSA()
34 src1 = (v16u8)__msa_ld_b((v16i8*)src_argb, 16); in ScaleARGBRowDown2_MSA()
51 src0 = (v16u8)__msa_ld_b((v16i8*)src_argb, 0); in ScaleARGBRowDown2Linear_MSA()
52 src1 = (v16u8)__msa_ld_b((v16i8*)src_argb, 16); in ScaleARGBRowDown2Linear_MSA()
71 v16i8 shuffler = {0, 4, 1, 5, 2, 6, 3, 7, 8, 12, 9, 13, 10, 14, 11, 15}; in ScaleARGBRowDown2Box_MSA()
74 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in ScaleARGBRowDown2Box_MSA()
75 src1 = (v16u8)__msa_ld_b((v16i8*)s, 16); in ScaleARGBRowDown2Box_MSA()
76 src2 = (v16u8)__msa_ld_b((v16i8*)t, 0); in ScaleARGBRowDown2Box_MSA()
77 src3 = (v16u8)__msa_ld_b((v16i8*)t, 16); in ScaleARGBRowDown2Box_MSA()
78 vec0 = (v16u8)__msa_vshf_b(shuffler, (v16i8)src0, (v16i8)src0); in ScaleARGBRowDown2Box_MSA()
[all …]
Drotate_msa.cc24 out0 = (v16u8)__msa_ilvr_b((v16i8)in1, (v16i8)in0); \
25 out1 = (v16u8)__msa_ilvl_b((v16i8)in1, (v16i8)in0); \
26 out2 = (v16u8)__msa_ilvr_b((v16i8)in3, (v16i8)in2); \
27 out3 = (v16u8)__msa_ilvl_b((v16i8)in3, (v16i8)in2); \
90 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
92 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
94 src2 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
96 src3 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
100 src0 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
102 src1 = (v16u8)__msa_ld_b((v16i8*)s, 0); in TransposeWx16_MSA()
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dvaddsplat.ll10 %v16i8 = type <16 x i8>
56 define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {
57 %p = load %v16i8, %v16i8* %P
58 …%r = add %v16i8 %p, < i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16,…
59 store %v16i8 %r, %v16i8* %S
67 define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {
68 %p = load %v16i8, %v16i8* %P
69 …%r = add %v16i8 %p, < i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -18, i8 -…
70 store %v16i8 %r, %v16i8* %S
126 define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Dloopfilter_16_msa.c84 v16i8 zero = { 0 }; in hz_lpf_t16_16w()
114 q0_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q0); in hz_lpf_t16_16w()
133 q0_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q0); in hz_lpf_t16_16w()
148 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in hz_lpf_t16_16w()
154 q1_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q1); in hz_lpf_t16_16w()
161 q1_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q1); in hz_lpf_t16_16w()
168 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in hz_lpf_t16_16w()
174 q2_r_in = (v8u16)__msa_ilvr_b(zero, (v16i8)q2); in hz_lpf_t16_16w()
181 q2_l_in = (v8u16)__msa_ilvl_b(zero, (v16i8)q2); in hz_lpf_t16_16w()
188 r_out = (v8i16)__msa_pckev_b((v16i8)l_out, (v16i8)r_out); in hz_lpf_t16_16w()
[all …]
Dmacros_msa.h21 #define LD_SB(...) LD_V(v16i8, __VA_ARGS__)
28 #define ST_SB(...) ST_V(v16i8, __VA_ARGS__)
241 #define LD_SB2(...) LD_V2(v16i8, __VA_ARGS__)
258 #define LD_SB4(...) LD_V4(v16i8, __VA_ARGS__)
267 #define LD_SB5(...) LD_V5(v16i8, __VA_ARGS__)
274 #define LD_SB7(...) LD_V7(v16i8, __VA_ARGS__)
283 #define LD_SB8(...) LD_V8(v16i8, __VA_ARGS__)
505 v16i8 zero_m = { 0 }; \
506 out0 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in0, slide_val); \
507 out1 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in1, slide_val); \
[all …]
Dvpx_convolve8_msa.c29 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_hv_8ht_8vt_4w_msa()
30 v16i8 filt_hz0, filt_hz1, filt_hz2, filt_hz3; in common_hv_8ht_8vt_4w_msa()
65 out2 = (v8i16)__msa_ilvev_b((v16i8)hz_out5, (v16i8)hz_out4); in common_hv_8ht_8vt_4w_msa()
74 hz_out6 = (v8i16)__msa_sldi_b((v16i8)hz_out7, (v16i8)hz_out5, 8); in common_hv_8ht_8vt_4w_msa()
75 out3 = (v8i16)__msa_ilvev_b((v16i8)hz_out7, (v16i8)hz_out6); in common_hv_8ht_8vt_4w_msa()
81 hz_out8 = (v8i16)__msa_sldi_b((v16i8)hz_out9, (v16i8)hz_out7, 8); in common_hv_8ht_8vt_4w_msa()
82 out4 = (v8i16)__msa_ilvev_b((v16i8)hz_out9, (v16i8)hz_out8); in common_hv_8ht_8vt_4w_msa()
103 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_hv_8ht_8vt_8w_msa()
104 v16i8 filt_hz0, filt_hz1, filt_hz2, filt_hz3; in common_hv_8ht_8vt_8w_msa()
156 out3 = (v8i16)__msa_ilvev_b((v16i8)hz_out7, (v16i8)hz_out6); in common_hv_8ht_8vt_8w_msa()
[all …]
Dvpx_convolve8_avg_msa.c20 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_hv_8ht_8vt_and_aver_dst_4w_msa()
22 v16i8 filt_hz0, filt_hz1, filt_hz2, filt_hz3; in common_hv_8ht_8vt_and_aver_dst_4w_msa()
56 vec2 = (v8i16)__msa_ilvev_b((v16i8)hz_out5, (v16i8)hz_out4); in common_hv_8ht_8vt_and_aver_dst_4w_msa()
67 hz_out6 = (v8i16)__msa_sldi_b((v16i8)hz_out7, (v16i8)hz_out5, 8); in common_hv_8ht_8vt_and_aver_dst_4w_msa()
68 vec3 = (v8i16)__msa_ilvev_b((v16i8)hz_out7, (v16i8)hz_out6); in common_hv_8ht_8vt_and_aver_dst_4w_msa()
74 hz_out8 = (v8i16)__msa_sldi_b((v16i8)hz_out9, (v16i8)hz_out7, 8); in common_hv_8ht_8vt_and_aver_dst_4w_msa()
75 vec4 = (v8i16)__msa_ilvev_b((v16i8)hz_out9, (v16i8)hz_out8); in common_hv_8ht_8vt_and_aver_dst_4w_msa()
98 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; in common_hv_8ht_8vt_and_aver_dst_8w_msa()
99 v16i8 filt_hz0, filt_hz1, filt_hz2, filt_hz3; in common_hv_8ht_8vt_and_aver_dst_8w_msa()
154 out3 = (v8i16)__msa_ilvev_b((v16i8)hz_out7, (v16i8)hz_out6); in common_hv_8ht_8vt_and_aver_dst_8w_msa()
[all …]
Dvpx_convolve_msa.h24 tmp_dpadd_0 = __msa_dotp_s_h((v16i8)vec0, (v16i8)filt0); \
25 tmp_dpadd_0 = __msa_dpadd_s_h(tmp_dpadd_0, (v16i8)vec1, (v16i8)filt1); \
26 tmp_dpadd_1 = __msa_dotp_s_h((v16i8)vec2, (v16i8)filt2); \
27 tmp_dpadd_1 = __msa_dpadd_s_h(tmp_dpadd_1, (v16i8)vec3, (v16i8)filt3); \
36 v16i8 vec0_m, vec1_m, vec2_m, vec3_m; \
54 v16i8 vec0_m, vec1_m, vec2_m, vec3_m, vec4_m, vec5_m, vec6_m, vec7_m; \
72 v16i8 vec0_m, vec1_m, vec2_m, vec3_m, vec4_m, vec5_m, vec6_m, vec7_m; \
108 tmp_m = (v16u8)__msa_pckev_b((v16i8)in0, (v16i8)in1); \
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h21 #define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
33 #define ST_SB(...) ST_B(v16i8, __VA_ARGS__)
274 #define LD_SB2(...) LD_B2(v16i8, __VA_ARGS__)
282 #define LD_SB3(...) LD_B3(v16i8, __VA_ARGS__)
290 #define LD_SB4(...) LD_B4(v16i8, __VA_ARGS__)
298 #define LD_SB5(...) LD_B5(v16i8, __VA_ARGS__)
307 #define LD_SB8(...) LD_B8(v16i8, __VA_ARGS__)
358 #define ST_SB4(...) ST_B4(v16i8, __VA_ARGS__)
514 v16i8 zero_m = { 0 }; \
516 out0 = (RTYPE)__msa_sldi_b((v16i8)zero_m, (v16i8)in0, slide_val); \
[all …]
Dsixtap_filter_msa.c38 v16i8 vec0_m, vec1_m, vec2_m; \
55 v16i8 vec0_m, vec1_m, vec2_m, vec3_m, vec4_m, vec5_m; \
69 v16i8 vec0_m, vec1_m, vec2_m, vec3_m, vec4_m, vec5_m, vec6_m, vec7_m; \
89 tmp0 = __msa_dotp_s_h((v16i8)vec0, (v16i8)filt0); \
90 tmp0 = __msa_dpadd_s_h(tmp0, (v16i8)vec1, (v16i8)filt1); \
97 v16i8 vec0_m, vec1_m; \
112 v16i8 vec0_m, vec1_m, vec2_m, vec3_m; \
123 v16i8 vec0_m, vec1_m, vec2_m, vec3_m; \
138 v16i8 src0, src1, src2, src3, filt0, filt1, filt2; in common_hz_6t_4x4_msa()
164 v16i8 src0, src1, src2, src3, filt0, filt1, filt2; in common_hz_6t_4x8_msa()
[all …]
Dmfqe_msa.c21 v16i8 src0 = { 0 }; in filter_by_weight8x8_msa()
22 v16i8 src1 = { 0 }; in filter_by_weight8x8_msa()
23 v16i8 dst0 = { 0 }; in filter_by_weight8x8_msa()
24 v16i8 dst1 = { 0 }; in filter_by_weight8x8_msa()
50 dst0 = (v16i8)__msa_pckev_b((v16i8)res_h_l, (v16i8)res_h_r); in filter_by_weight8x8_msa()
61 dst1 = (v16i8)__msa_pckev_b((v16i8)res_h_l, (v16i8)res_h_r); in filter_by_weight8x8_msa()
72 v16i8 src0, src1, src2, src3; in filter_by_weight16x16_msa()
73 v16i8 dst0, dst1, dst2, dst3; in filter_by_weight16x16_msa()
Dbilinear_filter_msa.c33 v16i8 src0, src1, src2, src3, mask; in common_hz_2t_4x4_msa()
54 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; in common_hz_2t_4x8_msa()
55 v16i8 res0, res1, res2, res3; in common_hz_2t_4x8_msa()
90 v16i8 src0, src1, src2, src3, mask; in common_hz_2t_8x4_msa()
112 v16i8 src0, src1, src2, src3, mask, out0, out1; in common_hz_2t_8x8mult_msa()
184 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; in common_hz_2t_16w_msa()
247 v16i8 src0, src1, src2, src3, src4; in common_vt_2t_4x4_msa()
248 v16i8 src10_r, src32_r, src21_r, src43_r, src2110, src4332; in common_vt_2t_4x4_msa()
264 src2110 = __msa_pckev_b((v16i8)tmp1, (v16i8)tmp0); in common_vt_2t_4x4_msa()
271 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; in common_vt_2t_4x8_msa()
[all …]
Dloopfilter_filters_msa.c21 p1_a_sub_q1 = (v16u8)__msa_srli_b((v16i8)p1_a_sub_q1, 1); \
29 v16i8 p1_m, p0_m, q0_m, q1_m, filt, q0_sub_p0, t1, t2; \
30 const v16i8 cnst4b = __msa_ldi_b(4); \
31 const v16i8 cnst3b = __msa_ldi_b(3); \
33 p1_m = (v16i8)__msa_xori_b(p1, 0x80); \
34 p0_m = (v16i8)__msa_xori_b(p0, 0x80); \
35 q0_m = (v16i8)__msa_xori_b(q0, 0x80); \
36 q1_m = (v16i8)__msa_xori_b(q1, 0x80); \
64 v16i8 p1_m, p0_m, q0_m, q1_m, filt, filt1, filt2; \
65 v16i8 q0_sub_p0; \
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td33 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
91 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
95 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
105 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
133 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
[all …]
/external/libvpx/libvpx/vp8/encoder/mips/msa/
Ddenoising_msa.c116 temp2_h = (v8i16)__msa_pckev_b((v16i8)temp3_h, (v16i8)temp2_h); in vp8_denoiser_filter_msa()
117 running_avg_y = (v16u8)__msa_pckev_b((v16i8)temp1_h, (v16i8)temp0_h); in vp8_denoiser_filter_msa()
164 temp2_h = (v8i16)__msa_pckev_b((v16i8)temp3_h, (v16i8)temp2_h); in vp8_denoiser_filter_msa()
165 running_avg_y = (v16u8)__msa_pckev_b((v16i8)temp1_h, (v16i8)temp0_h); in vp8_denoiser_filter_msa()
238 running_avg_y = (v16u8)__msa_pckev_b((v16i8)adjust3, (v16i8)adjust2); in vp8_denoiser_filter_msa()
272 running_avg_y = (v16u8)__msa_pckev_b((v16i8)adjust3, (v16i8)adjust2); in vp8_denoiser_filter_msa()
331 v16i8 zero = { 0 }; in vp8_denoiser_filter_uv_msa()
338 temp0_h = (v8i16)__msa_ilvr_b(zero, (v16i8)sig0); in vp8_denoiser_filter_uv_msa()
341 temp0_h += (v8i16)__msa_ilvr_b(zero, (v16i8)sig1); in vp8_denoiser_filter_uv_msa()
344 temp0_h += (v8i16)__msa_ilvr_b(zero, (v16i8)sig2); in vp8_denoiser_filter_uv_msa()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/useful-harnesses/
Dvecoperations.c3 typedef unsigned char v16i8 __attribute__((ext_vector_type(16))); typedef
10 void print_v16i8(const char *str, const v16i8 v) { in print_v16i8()
13 v16i8 vec; in print_v16i8()
24 void print_v16i8_hex(const char *str, const v16i8 v) { in print_v16i8_hex()
27 v16i8 vec; in print_v16i8_hex()
68 v16i8 v16i8_mpy(v16i8 v1, v16i8 v2) { in v16i8_mpy()
72 v16i8 v16i8_add(v16i8 v1, v16i8 v2) { in v16i8_add()
137 v16i8 v00 = { 0xf4, 0xad, 0x01, 0xe9, 0x51, 0x78, 0xc1, 0x8a, in main()
139 v16i8 va0 = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, in main()
141 v16i8 va1 = { 0x11, 0x83, 0x4b, 0x63, 0xff, 0x90, 0x32, 0xe5, in main()
/external/libpng/mips/
Dfilter_msa_intrinsics.c42 #define MSA_SRLI_B(a, b) __msa_srli_b((v16i8) a, b)
300 out0 = (RTYPE) __msa_ilvr_b((v16i8) in0, (v16i8) in1); \
301 out1 = (RTYPE) __msa_ilvr_b((v16i8) in2, (v16i8) in3); \
314 v16i8 zero_m = { 0 }; \
315 out0 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in0, slide_val); \
316 out1 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in1, slide_val); \
322 v16i8 zero_m = { 0 }; \
324 out2 = (RTYPE) __msa_sldi_b((v16i8) zero_m, (v16i8) in2, slide_val); \
347 out0 = (RTYPE) __msa_vshf_b((v16i8) mask0, (v16i8) in1, (v16i8) in0); \
348 out1 = (RTYPE) __msa_vshf_b((v16i8) mask1, (v16i8) in3, (v16i8) in2); \
[all …]
/external/webp/src/dsp/
Dmsa_macro.h28 #define SRAI_B(a, b) __msa_srai_b((v16i8)a, b)
50 #define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
62 #define ST_SB(...) ST_B(v16i8, __VA_ARGS__)
225 #define LD_SB2(...) LD_B2(v16i8, __VA_ARGS__)
232 #define LD_SB3(...) LD_B3(v16i8, __VA_ARGS__)
239 #define LD_SB4(...) LD_B4(v16i8, __VA_ARGS__)
247 #define LD_SB8(...) LD_B8(v16i8, __VA_ARGS__)
301 #define ST_SB2(...) ST_B2(v16i8, __VA_ARGS__)
308 #define ST_SB4(...) ST_B4(v16i8, __VA_ARGS__)
417 (RTYPE)__msa_sldi_b((v16i8)in0, (v16i8)in1, slide_val) \
[all …]
/external/libvpx/libvpx/vp9/common/mips/msa/
Dvp9_mfqe_msa.c21 v16i8 src0 = { 0 }; in filter_by_weight8x8_msa()
22 v16i8 src1 = { 0 }; in filter_by_weight8x8_msa()
23 v16i8 dst0 = { 0 }; in filter_by_weight8x8_msa()
24 v16i8 dst1 = { 0 }; in filter_by_weight8x8_msa()
50 dst0 = (v16i8)__msa_pckev_b((v16i8)res_h_l, (v16i8)res_h_r); in filter_by_weight8x8_msa()
61 dst1 = (v16i8)__msa_pckev_b((v16i8)res_h_l, (v16i8)res_h_r); in filter_by_weight8x8_msa()
72 v16i8 src0, src1, src2, src3, dst0, dst1, dst2, dst3; in filter_by_weight16x16_msa()
/external/clang/test/CodeGen/
Dbuiltins-systemz-error2.c4 typedef __attribute__((vector_size(16))) char v16i8; typedef
6 v16i8 f0(v16i8 a, v16i8 b) { in f0()
8 …v16i8 tmp = __builtin_s390_vaq(a, b); // expected-error {{'__builtin_s390_vaq' needs target featur… in f0()
/external/libyuv/files/include/libyuv/
Dmacros_msa.h212 out0 = (RTYPE)__msa_vshf_b((v16i8)mask0, (v16i8)in1, (v16i8)in0); \
213 out1 = (RTYPE)__msa_vshf_b((v16i8)mask1, (v16i8)in3, (v16i8)in2); \
226 out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
227 out1 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrAltivec.td18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
297 (vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>;
[all …]
/external/gemmlowp/internal/
Dpack_msa.h53 v16i8 src_lines[4 * kCells]; in Pack()
59 v16i8 src_lines_intertwined_2x[2 * kCells][2]; in Pack()
70 v16i8 src_lines_intertwined_4x[2 * kCells][2]; in Pack()
95 __builtin_msa_st_b(reinterpret_cast<v16i8>(tmp), dst_ptr, 0); in Pack()
104 __builtin_msa_st_b(reinterpret_cast<v16i8>(tmp), dst_ptr, 0); in Pack()
115 __builtin_msa_st_b(reinterpret_cast<v16i8>(tmp), dst_ptr, 0); in Pack()
125 __builtin_msa_st_b(reinterpret_cast<v16i8>(tmp), dst_ptr, 0); in Pack()
134 __builtin_msa_st_b(reinterpret_cast<v16i8>(tmp), dst_ptr, 0); in Pack()
142 const v16i8 zeroes = __builtin_msa_ldi_b(0); in Pack()
258 __builtin_msa_st_b(reinterpret_cast<v16i8>(tmp), dst_ptr, 0); in Pack()
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-tbl.ll13 %tmp3 = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> %A, <16 x i8> %B)
27 %tmp3 = call <16 x i8> @llvm.aarch64.neon.tbl2.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C)
41 …%tmp3 = call <16 x i8> @llvm.aarch64.neon.tbl3.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16…
55 …%tmp3 = call <16 x i8> @llvm.aarch64.neon.tbl4.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16…
60 declare <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
62 declare <16 x i8> @llvm.aarch64.neon.tbl2.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
64 declare <16 x i8> @llvm.aarch64.neon.tbl3.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) nounwin…
66 declare <16 x i8> @llvm.aarch64.neon.tbl4.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i…
78 %tmp3 = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C)
92 …%tmp3 = call <16 x i8> @llvm.aarch64.neon.tbx2.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16…
[all …]

12345678910>>...13