Searched refs:v1i16 (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 78 v1i16 = 30, // 1 x i16 enumerator
228 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
334 case v1i16: in getVectorElementType()
420 case v1i16: in getVectorNumElements()
458 case v1i16: return 16; in getSizeInBits()
614 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
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| D | ValueTypes.td | 55 def v1i16 : ValueType<16 , 30>; // 1 x i16 vector value
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| /external/clang/test/CodeGen/ |
| D | systemz-abi-vector.c | 13 typedef __attribute__((vector_size(2))) short v1i16; typedef
66 v1i16 pass_v1i16(v1i16 arg) { return arg; } in pass_v1i16()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | trunc-v1i64.ll | 6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
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| D | arm64-neon-copy.ll | 857 define <8 x i16> @testDUP.v1i16(<1 x i16> %a) {
858 ; CHECK-LABEL: testDUP.v1i16:
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 162 case MVT::v1i16: return "v1i16"; in getEVTString()
240 case MVT::v1i16: return VectorType::get(Type::getInt16Ty(Context), 1); in getTypeForEVT()
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| /external/llvm/test/CodeGen/ARM/ |
| D | cttz_vector.ll | 11 declare <1 x i16> @llvm.cttz.v1i16(<1 x i16>, i1)
82 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)
266 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 344 // D form - v1i8, v1i16, v1i32, v1i64
371 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
407 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
497 // D form - v1i8, v1i16, v1i32, v1i64
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| D | AArch64SchedKryoDetails.td | 214 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
232 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
262 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
274 (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>;
1799 (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>;
1805 (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>;
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| D | AArch64InstrFormats.td | 5688 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
5701 def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
5709 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
5929 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
5941 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
5956 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5971 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
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| D | AArch64ISelLowering.cpp | 10163 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 in getPreferredVectorAction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 90 case MVT::v1i16: return "MVT::v1i16"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 188 def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16
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