Home
last modified time | relevance | path

Searched refs:v32i1 (Results 1 – 11 of 11) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h63 v32i1 = 17, // 32 x i1 enumerator
321 case v32i1: in getVectorElementType()
384 case v32i1: in getVectorNumElements()
461 case v32i1: in getSizeInBits()
597 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
DValueTypes.td40 def v32i1 : ValueType<32 , 17>; // 32 x i1 vector value
/external/llvm/lib/IR/
DValueTypes.cpp149 case MVT::v32i1: return "v32i1"; in getEVTString()
227 case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp77 case MVT::v32i1: return "MVT::v32i1"; in getEnumName()
/external/llvm/lib/Target/X86/
DX86CallingConv.td50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
327 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
600 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
DX86RegisterInfo.td516 def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
524 def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
DX86InstrAVX512.td1984 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2016 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2017 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2078 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2080 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2156 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2233 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2334 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2374 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2440 defm D : avx512_mask_setop<VK32, v32i1, Val>;
[all …]
DX86ISelLowering.cpp1391 MVT::v16i1, MVT::v32i1, MVT::v64i1 }) in X86TargetLowering()
1416 addRegisterClass(MVT::v32i1, &X86::VK32RegClass); in X86TargetLowering()
1419 setOperationAction(ISD::ADD, MVT::v32i1, Expand); in X86TargetLowering()
1421 setOperationAction(ISD::SUB, MVT::v32i1, Expand); in X86TargetLowering()
1423 setOperationAction(ISD::MUL, MVT::v32i1, Expand); in X86TargetLowering()
1426 setOperationAction(ISD::SETCC, MVT::v32i1, Custom); in X86TargetLowering()
1432 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom); in X86TargetLowering()
1436 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom); in X86TargetLowering()
1444 setOperationAction(ISD::SELECT, MVT::v32i1, Custom); in X86TargetLowering()
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom); in X86TargetLowering()
[all …]
DX86InstrCompiler.td565 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
/external/llvm/include/llvm/IR/
DIntrinsics.td173 def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1975 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1, in HexagonTargetLowering()