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Searched refs:val32 (Results 1 – 25 of 40) sorted by relevance

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/external/elfutils/libdwfl/
Dlinux-core-attach.c153 uint32_t val32 = read_4ubyte_unaligned_noncvt (desc + item->offset); in core_next_thread() local
154 val32 = (elf_getident (core, NULL)[EI_DATA] == ELFDATA2MSB in core_next_thread()
155 ? be32toh (val32) : le32toh (val32)); in core_next_thread()
156 pid_t tid = (int32_t) val32; in core_next_thread()
157 eu_static_assert (sizeof val32 <= sizeof tid); in core_next_thread()
204 uint32_t val32 = read_4ubyte_unaligned_noncvt (desc + item->offset); in core_set_initial_registers() local
205 val32 = (elf_getident (core, NULL)[EI_DATA] == ELFDATA2MSB in core_set_initial_registers()
206 ? be32toh (val32) : le32toh (val32)); in core_set_initial_registers()
207 tid = (int32_t) val32; in core_set_initial_registers()
208 eu_static_assert (sizeof val32 <= sizeof tid); in core_set_initial_registers()
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/external/mesa3d/src/gallium/drivers/ilo/shader/
Dtoy_compiler_reg.h129 uint32_t val32; member
150 uint32_t val32; member
217 return (dst.file == TOY_FILE_ARF && dst.val32 == 0); in tdst_is_null()
232 assert(dst.val32 < toy_file_size(dst.file)); in tdst_validate()
236 assert(dst.val32 < toy_file_size(dst.file)); in tdst_validate()
258 assert(dst.val32 % toy_type_size(dst.type) == 0); in tdst_validate()
338 dst.val32 += reg * TOY_REG_WIDTH + subreg * toy_type_size(dst.type); in tdst_offset()
348 enum toy_writemask writemask, uint32_t val32) in tdst_full() argument
360 dst.val32 = val32; in tdst_full()
379 .val32 = 0, in tdst_null()
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Dtoy_legalize_ra.c385 const uint32_t mdesc = inst->src[1].val32; in linear_scan_init_live_intervals()
396 vrf = inst->dst.val32 / TOY_REG_WIDTH; in linear_scan_init_live_intervals()
414 vrf = inst->src[i].val32 / TOY_REG_WIDTH; in linear_scan_init_live_intervals()
531 const uint32_t val32 = inst->dst.val32; in linear_scan_allocation() local
532 int reg = val32 / TOY_REG_WIDTH; in linear_scan_allocation()
533 int subreg = val32 % TOY_REG_WIDTH; in linear_scan_allocation()
539 inst->dst.val32 = reg * TOY_REG_WIDTH + subreg; in linear_scan_allocation()
543 const uint32_t val32 = inst->src[i].val32; in linear_scan_allocation() local
549 reg = val32 / TOY_REG_WIDTH; in linear_scan_allocation()
550 subreg = val32 % TOY_REG_WIDTH; in linear_scan_allocation()
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Dtoy_compiler.c36 bool indirect, unsigned indirect_subreg, uint32_t val32, in tc_dump_operand() argument
50 reg = val32 / TOY_REG_WIDTH; in tc_dump_operand()
51 subreg = (val32 % TOY_REG_WIDTH) / toy_type_size(type); in tc_dump_operand()
60 if (val32) in tc_dump_operand()
61 ilo_printf("%+d", (int) val32); in tc_dump_operand()
106 union fi fi = { .ui = val32 }; in tc_dump_operand()
111 ilo_printf("%d", (int32_t) val32); in tc_dump_operand()
114 ilo_printf("%u", val32); in tc_dump_operand()
117 ilo_printf("%d", (int16_t) (val32 & 0xffff)); in tc_dump_operand()
120 ilo_printf("%u", val32 & 0xffff); in tc_dump_operand()
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Dilo_shader_vs.c87 const int i = idx.val32; in vs_lower_opcode_tgsi_const_pcb()
236 dim = inst->src[0].val32; in vs_lower_opcode_tgsi_direct()
239 idx = inst->src[1].val32; in vs_lower_opcode_tgsi_direct()
276 file = inst->src[0].val32; in vs_lower_opcode_tgsi_indirect()
279 dim = inst->src[1].val32; in vs_lower_opcode_tgsi_indirect()
283 idx = inst->src[3].val32; in vs_lower_opcode_tgsi_indirect()
288 dim += indirect_dim.val32; in vs_lower_opcode_tgsi_indirect()
507 sampler_index = inst->src[sampler_src].val32; in vs_prepare_tgsi_sampling()
Dtoy_legalize.c192 inst->src[i].val32 = in validate_imm()
193 absolute_imm(inst->src[i].val32, inst->src[i].type); in validate_imm()
198 inst->src[i].val32 = in validate_imm()
199 negate_imm(inst->src[i].val32, inst->src[i].type); in validate_imm()
/external/webrtc/webrtc/base/
Dbitbuffer_unittest.cc45 uint32_t val32; in TEST() local
53 EXPECT_TRUE(buffer.ReadUInt32(&val32)); in TEST()
54 EXPECT_EQ(0x23456789u, val32); in TEST()
62 uint32_t val32; in TEST() local
72 EXPECT_TRUE(buffer.ReadUInt32(&val32)); in TEST()
73 EXPECT_EQ(0x34567890u, val32); in TEST()
97 uint32_t val32; in TEST() local
104 EXPECT_TRUE(buffer.ReadUInt32(&val32)); in TEST()
105 EXPECT_EQ(0x98765432u, val32); in TEST()
292 uint32_t val32; in TEST() local
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/external/llvm/test/CodeGen/NVPTX/
Dhalf.ll37 %val32 = fpext half %val16 to float
38 store float %val32, float addrspace(1)* %out
56 %val32 = load float, float addrspace(1)* %in
57 %val16 = fptrunc float %val32 to half
66 %val32 = load double, double addrspace(1)* %in
67 %val16 = fptrunc double %val32 to half
/external/llvm/test/CodeGen/AArch64/
Daddsub.ll16 %val32 = load i32, i32* @var_i32
17 %newval32 = add i32 %val32, 4095
61 %val32 = load i32, i32* @var_i32
62 %newval32 = add i32 %val32, 14610432 ; =0xdef000
78 %val32 = load i32, i32* @var_i32
79 %newval32 = sub i32 %val32, 4095
95 %val32 = load i32, i32* @var_i32
96 %newval32 = sub i32 %val32, 14610432 ; =0xdef000
Darm64-fp128.ll65 %val32 = fptosi fp128 %val to i32
66 store i32 %val32, i32* @var32
80 %val32 = fptoui fp128 %val to i32
81 store i32 %val32, i32* @var32
95 %val32 = sitofp i32 %src32 to fp128
96 store volatile fp128 %val32, fp128* @lhs
111 %val32 = uitofp i32 %src32 to fp128
112 store volatile fp128 %val32, fp128* @lhs
Dhalf.ll54 %val32 = fpext half %val16 to float
55 ret float %val32
63 %val32 = fpext half %val16 to double
64 ret double %val32
Dbitfield.ll83 define void @test_shifts(i32 %val32, i64 %val64) {
86 %shift1 = ashr i32 %val32, 31
90 %shift2 = lshr i32 %val32, 8
94 %shift3 = shl i32 %val32, 1
118 %shift9 = lshr i32 %val32, 31
122 %shift10 = shl i32 %val32, 31
Darm64-register-offset-addressing.ll68 %val32 = load volatile i32, i32* @var_32bit
69 %val16_trunc32 = trunc i32 %val32 to i16
103 %val32 = load volatile i32, i32* @var_32bit
104 store volatile i32 %val32, i32* %addr_uxtwN
Dfloatdp_1source.ll110 %val32 = load volatile float, float* @varfloat
121 %val32to16 = fptrunc float %val32 to half
125 %val32to64 = fpext float %val32 to double
Daddsub_ext.ll282 %val32 = add i32 %val32_tmp, 123
284 %rhs64_zext = zext i32 %val32 to i64
294 %rhs64_sext = sext i32 %val32 to i64
312 %val32 = add i32 %val32_tmp, 123
314 %rhs64_zext = zext i32 %val32 to i64
324 %rhs64_sext = sext i32 %val32 to i64
Dldst-unscaledimm.ll60 %val32 = load volatile i32, i32* @var_32bit
61 %val8_trunc32 = trunc i32 %val32 to i8
127 %val32 = load volatile i32, i32* @var_32bit
128 %val16_trunc32 = trunc i32 %val32 to i16
/external/deqp/framework/delibs/debase/
DdeFloat16.c28 deFloat16 deFloat32To16 (float val32) in deFloat32To16() argument
39 x.f = val32; in deFloat32To16()
138 deFloat16 deFloat32To16Round (float val32, deRoundingMode mode) in deFloat32To16Round() argument
153 x.f = val32; in deFloat32To16Round()
DdeFloat16.h42 deFloat16 deFloat32To16 (float val32);
43 deFloat16 deFloat32To16Round (float val32, deRoundingMode mode);
DdeFloat16Test.c48 static deFloat16 deFloat32To16RTZ (float val32) in deFloat32To16RTZ() argument
50 return deFloat32To16Round(val32, DE_ROUNDINGMODE_TO_ZERO); in deFloat32To16RTZ()
53 static deFloat16 deFloat32To16RTE (float val32) in deFloat32To16RTE() argument
55 return deFloat32To16Round(val32, DE_ROUNDINGMODE_TO_NEAREST_EVEN); in deFloat32To16RTE()
/external/llvm/test/CodeGen/ARM/
Dhalf.ll37 %val32 = fpext half %val16 to float
38 ret float %val32
50 %val32 = fpext half %val16 to double
51 ret double %val32
/external/llvm/test/CodeGen/MIR/AArch64/
Dexpected-target-flag-name.mir10 %val32 = load i32, i32* @var_i32
11 ret i32 %val32
Dinvalid-target-flag-name.mir10 %val32 = load i32, i32* @var_i32
11 ret i32 %val32
Dtarget-flags.mir10 %val32 = load i32, i32* @var_i32
11 %newval32 = sub i32 %val32, 4095
/external/perf_data_converter/src/quipper/
Dsample_info_reader.cc346 uint32_t val32[sizeof(uint64_t) / sizeof(uint32_t)]; in WritePerfSampleToData() member
370 val32[0] = sample.pid; in WritePerfSampleToData()
371 val32[1] = sample.tid; in WritePerfSampleToData()
397 val32[0] = sample.cpu; in WritePerfSampleToData()
399 val32[1] = 0; in WritePerfSampleToData()
/external/llvm/test/MC/AArch64/
Delf-globaladdress.ll21 %val32 = load i32, i32* @var32
22 store volatile i32 %val32, i32* @var32

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