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Searched refs:val4 (Results 1 – 25 of 105) sorted by relevance

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/external/llvm/test/CodeGen/SystemZ/
Dvec-cmp-03.ll112 <4 x i32> %val3, <4 x i32> %val4) {
118 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
124 <4 x i32> %val3, <4 x i32> %val4) {
130 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
136 <4 x i32> %val3, <4 x i32> %val4) {
142 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
148 <4 x i32> %val3, <4 x i32> %val4) {
154 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
160 <4 x i32> %val3, <4 x i32> %val4) {
166 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
[all …]
Dvec-cmp-02.ll112 <8 x i16> %val3, <8 x i16> %val4) {
118 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
124 <8 x i16> %val3, <8 x i16> %val4) {
130 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
136 <8 x i16> %val3, <8 x i16> %val4) {
142 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
148 <8 x i16> %val3, <8 x i16> %val4) {
154 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
160 <8 x i16> %val3, <8 x i16> %val4) {
166 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
[all …]
Dvec-cmp-01.ll112 <16 x i8> %val3, <16 x i8> %val4) {
118 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
124 <16 x i8> %val3, <16 x i8> %val4) {
130 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
136 <16 x i8> %val3, <16 x i8> %val4) {
142 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
148 <16 x i8> %val3, <16 x i8> %val4) {
154 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
160 <16 x i8> %val3, <16 x i8> %val4) {
166 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
[all …]
Dvec-cmp-04.ll112 <2 x i64> %val3, <2 x i64> %val4) {
118 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
124 <2 x i64> %val3, <2 x i64> %val4) {
130 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
136 <2 x i64> %val3, <2 x i64> %val4) {
142 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
148 <2 x i64> %val3, <2 x i64> %val4) {
154 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
160 <2 x i64> %val3, <2 x i64> %val4) {
166 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
[all …]
Dvec-cmp-06.ll165 <2 x double> %val3, <2 x double> %val4) {
171 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
177 <2 x double> %val3, <2 x double> %val4) {
185 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
191 <2 x double> %val3, <2 x double> %val4) {
197 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
203 <2 x double> %val3, <2 x double> %val4) {
209 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
215 <2 x double> %val3, <2 x double> %val4) {
221 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
[all …]
Dvec-cmp-05.ll308 <4 x float> %val3, <4 x float> %val4) {
314 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
320 <4 x float> %val3, <4 x float> %val4) {
326 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
332 <4 x float> %val3, <4 x float> %val4) {
338 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
344 <4 x float> %val3, <4 x float> %val4) {
350 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
356 <4 x float> %val3, <4 x float> %val4) {
362 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
[all …]
Dspill-01.ll51 %val4 = load i32 , i32 *%ptr4
61 store i32 %val4, i32 *%ptr4
89 %val4 = load i32 , i32 *%ptr4
101 store i32 %val4, i32 *%ptr4
131 %val4 = load i64 , i64 *%ptr4
143 store i64 %val4, i64 *%ptr4
177 %val4 = load float , float *%ptr4
190 store float %val4, float *%ptr4
221 %val4 = load double , double *%ptr4
234 store double %val4, double *%ptr4
[all …]
Dint-add-11.ll141 %val4 = load volatile i32 , i32 *%ptr
162 %add4 = add i32 %val4, 127
181 %new4 = phi i32 [ %val4, %entry ], [ %add4, %add ]
224 %val4 = load volatile i32 , i32 *%ptr
245 %add4 = add i32 %val4, -128
264 %new4 = phi i32 [ %val4, %entry ], [ %add4, %add ]
Dint-add-12.ll140 %val4 = load volatile i64 , i64 *%ptr
161 %add4 = add i64 %val4, 127
180 %new4 = phi i64 [ %val4, %entry ], [ %add4, %add ]
223 %val4 = load volatile i64 , i64 *%ptr
244 %add4 = add i64 %val4, -128
263 %new4 = phi i64 [ %val4, %entry ], [ %add4, %add ]
/external/llvm/test/CodeGen/AArch64/
Dfloatdp_2source.ll16 %val4 = fdiv float %val3, %val1
19 %val5 = fsub float %val4, %val2
44 %val4 = fdiv double %val3, %val1
47 %val5 = fsub double %val4, %val2
Dcompare-branch.ll27 %val4 = load volatile i64, i64* @var64
28 %tst4 = icmp ne i64 %val4, 0
33 store volatile i64 %val4, i64* @var64
Daddsub-shifted.ll30 %val4 = sub i32 %shift4, %lhs32
31 store volatile i32 %val4, i32* @var32
95 %val4 = sub i32 %shift4, %lhs32
96 store volatile i32 %val4, i32* @var32
154 %val4 = sub i32 %shift4, %lhs32
155 store volatile i32 %val4, i32* @var32
273 %val4 = sub i64 0, %shift4
274 %tst4 = icmp slt i64 %lhs64, %val4
Dregress-w29-reserved-with-fp.ll13 %val4 = load volatile i32, i32* @var
28 store volatile i32 %val4, i32* @var
Dcond-sel.ll89 %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
90 store volatile i64 %val4, i64* @var64
129 %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
130 store volatile i64 %val4, i64* @var64
197 %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
198 store volatile i64 %val4, i64* @var64
/external/tensorflow/tensorflow/compiler/tests/
Ddynamic_stitch_test.py65 val4 = np.array([10, 60, 20, 30, 50], dtype=np.float32)
68 [val1, val2], [val3, val4], expected=expected)
74 val4 = np.array([[0, 1], [40, 41], [70, 71]], dtype=np.float32)
82 [val1, val2, val3], [val4, val5, val6], expected=expected)
/external/swiftshader/third_party/LLVM/include/llvm/Support/
DFormat.h141 const T3 &val3, const T4 &val4) in format_object4() argument
142 : format_object_base(fmt), Val1(val1), Val2(val2), Val3(val3), Val4(val4) { in format_object4()
163 const T3 &val3, const T4 &val4, const T5 &val5) in format_object5() argument
164 : format_object_base(fmt), Val1(val1), Val2(val2), Val3(val3), Val4(val4), in format_object5()
/external/deqp/framework/delibs/debase/
DdeSha1.c217 deUint8 val4; in deSha1_parse() local
220 val4 = (deUint8)(buffer[charNdx] - '0'); in deSha1_parse()
222 val4 = (deUint8)(10 + (buffer[charNdx] - 'a')); in deSha1_parse()
224 val4 = (deUint8)(10 + (buffer[charNdx] - 'A')); in deSha1_parse()
228 hash->hash[charNdx / 8] |= ((deUint32)val4) << (4 * (8u - 1u - (charNdx % 8u))); in deSha1_parse()
/external/swiftshader/third_party/LLVM/test/Transforms/SimplifyLibCalls/
DIsDigit.ll13 %val4 = call i32 @isdigit( i32 58 ) ; <i32> [#uses=1]
15 %rslt2 = add i32 %val3, %val4 ; <i32> [#uses=1]
DToAscii.ll11 %val4 = call i32 @toascii( i32 128 ) ; <i32> [#uses=1]
15 %rslt2 = add i32 %val3, %val4 ; <i32> [#uses=1]
DFFS.ll19 %val4 = call i32 @ffsll( i64 1024 ) ; <i32> [#uses=1]
23 %rslt2 = add i32 %val3, %val4 ; <i32> [#uses=1]
/external/llvm/test/CodeGen/ARM/
Dinlineasm-64bit.ll13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6…
37 … [$0]\0A", "r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %va…
39 …, "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %va…
40 …, "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %va…
Dgpr-paired-spill-thumbinst.ll12 %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
25 store volatile i64 %val4, i64* %addr
Dvldm-liveness.ll30 %val4 = load float, float* %off4
36 %vec3 = insertelement <4 x float> %vec2, float %val4, i32 2
/external/llvm/test/CodeGen/AMDGPU/
Dds_read2_offset_order.ll33 %val4 = load float, float addrspace(3)* %ptr4
34 %add4 = fadd float %add3, %val4
/external/llvm/test/CodeGen/Mips/
Dnacl-reserved-regs.ll11 %val4 = load volatile i32, i32* @var
27 store volatile i32 %val4, i32* @var

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