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Searched refs:vceq (Results 1 – 25 of 40) sorted by relevance

12

/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-cmp-encoding.s3 vceq.i8 d16, d16, d17
4 vceq.i16 d16, d16, d17
5 vceq.i32 d16, d16, d17
6 vceq.f32 d16, d16, d17
7 vceq.i8 q8, q8, q9
8 vceq.i16 q8, q8, q9
9 vceq.i32 q8, q8, q9
10 vceq.f32 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
13 @ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3]
[all …]
/external/llvm/test/MC/ARM/
Dneon-cmp-encoding.s3 vceq.i8 d16, d16, d17
4 vceq.i16 d16, d16, d17
5 vceq.i32 d16, d16, d17
6 vceq.f32 d16, d16, d17
7 vceq.i8 q8, q8, q9
8 vceq.i16 q8, q8, q9
9 vceq.i32 q8, q8, q9
10 vceq.f32 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
13 @ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3]
[all …]
Dfullfp16-neon.s74 vceq.f16 d2, d3, d4
75 vceq.f16 q2, q3, q4
76 @ ARM: vceq.f16 d2, d3, d4 @ encoding: [0x04,0x2e,0x13,0xf2]
77 @ ARM: vceq.f16 q2, q3, q4 @ encoding: [0x48,0x4e,0x16,0xf2]
78 @ THUMB: vceq.f16 d2, d3, d4 @ encoding: [0x13,0xef,0x04,0x2e]
79 @ THUMB: vceq.f16 q2, q3, q4 @ encoding: [0x16,0xef,0x48,0x4e]
81 vceq.f16 d2, d3, #0
82 vceq.f16 q2, q3, #0
83 @ ARM: vceq.f16 d2, d3, #0 @ encoding: [0x03,0x25,0xb5,0xf3]
84 @ ARM: vceq.f16 q2, q3, #0 @ encoding: [0x46,0x45,0xb5,0xf3]
[all …]
Dfullfp16-neon-neg.s56 vceq.f16 d2, d3, d4
57 vceq.f16 q2, q3, q4
61 vceq.f16 d2, d3, #0
62 vceq.f16 q2, q3, #0
Dneon-bitwise-encoding.s307 vceq.s16 q5, q3
308 vceq.s16 d5, d3
322 vceq.s16 q5, #0
323 vceq.s16 d5, #0
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvceq.ll5 ;CHECK: vceq.i8
15 ;CHECK: vceq.i16
25 ;CHECK: vceq.i32
35 ;CHECK: vceq.f32
45 ;CHECK: vceq.i8
55 ;CHECK: vceq.i16
65 ;CHECK: vceq.i32
75 ;CHECK: vceq.f32
87 ;CHECK: vceq.i8
Dvicmp.ll11 ;CHECK: vceq.i8
22 ;CHECK: vceq.i16
33 ;CHECK: vceq.i32
44 ;CHECK: vceq.i8
55 ;CHECK: vceq.i16
66 ;CHECK: vceq.i32
Dvfcmp.ll8 ;CHECK: vceq.f32
/external/capstone/suite/MC/ARM/
Dneon-cmp-encoding.s.cs2 0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17
3 0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17
4 0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17
5 0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17
6 0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9
7 0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9
8 0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9
9 0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9
48 0x20,0x01,0xf1,0xf3 = vceq.i8 d16, d16, #0
Dneon-bitwise-encoding.s.cs109 0x56,0xa8,0x1a,0xf3 = vceq.i16 q5, q5, q3
110 0x13,0x58,0x15,0xf3 = vceq.i16 d5, d5, d3
119 0x4a,0xa1,0xb5,0xf3 = vceq.i16 q5, q5, #0
120 0x05,0x51,0xb5,0xf3 = vceq.i16 d5, d5, #0
/external/llvm/test/CodeGen/ARM/
Dvceq.ll5 ;CHECK: vceq.i8
15 ;CHECK: vceq.i16
25 ;CHECK: vceq.i32
35 ;CHECK: vceq.f32
45 ;CHECK: vceq.i8
55 ;CHECK: vceq.i16
65 ;CHECK: vceq.i32
75 ;CHECK: vceq.f32
87 ;CHECK: vceq.i8
Dvicmp.ll11 ;CHECK: vceq.i8
22 ;CHECK: vceq.i16
33 ;CHECK: vceq.i32
44 ;CHECK: vceq.i8
55 ;CHECK: vceq.i16
66 ;CHECK: vceq.i32
Dsetcc-type-mismatch.ll5 ; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}}
Dvfcmp.ll8 ;CHECK: vceq.f32
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Dcmp-vec.ll29 ; ASM: vceq.i32 q0, q0, q1
31 ; IASM-NOT: vceq
45 ; ASM: vceq.i32 q0, q0, q1
49 ; IASM-NOT: vceq
196 ; ASM-NEXT: vceq.i32 q0, q0, q1
201 ; IASM-NOT: vceq
219 ; ASM-NEXT: vceq.i32 q0, q0, q1
226 ; IASM-NOT: vceq
425 ; ASM: vceq.i16 q0, q0, q1
427 ; IASM-NOT: vceq
[all …]
/external/arm-neon-tests/
Dref_vceq.c26 #define INSN_NAME vceq
DAndroid.mk25 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
DMakefile.gcc46 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
DMakefile40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-arm.txt54 # CHECK: vceq.f16 d2, d3, d4
55 # CHECK: vceq.f16 q2, q3, q4
59 # CHECK: vceq.f16 d2, d3, #0
60 # CHECK: vceq.f16 q2, q3, #0
Dfullfp16-neon-thumb.txt54 # CHECK: vceq.f16 d2, d3, d4
55 # CHECK: vceq.f16 q2, q3, q4
59 # CHECK: vceq.f16 d2, d3, #0
60 # CHECK: vceq.f16 q2, q3, #0
/external/libavc/common/arm/
Dih264_resi_trans_quant_a9.s215 vceq.s16 q5, q15, #0 @I compare with zero row 1 and 2 blk 1
216 vceq.s16 q6, q0 , #0 @I compare with zero row 1 and 2 blk 1
410 vceq.s16 q5, q15, #0 @I compare with zero row 1 and 2 blk 1
411 vceq.s16 q6, q0 , #0 @I compare with zero row 1 and 2 blk 1
557 vceq.s16 q5, q11, #0
558 vceq.s16 q6, q12, #0
673 vceq.s16 q7, q4, #0 @Compute nnz
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc1548 __ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
1554 __ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); in AssembleArchInstruction() local
1620 __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
1626 __ vceq(Neon32, dst, i.InputSimd128Register(0), in AssembleArchInstruction() local
1732 __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
1738 __ vceq(Neon16, dst, i.InputSimd128Register(0), in AssembleArchInstruction() local
1854 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
1860 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); in AssembleArchInstruction() local
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon.txt330 # CHECK: vceq.i8 d16, d16, d17
331 # CHECK: vceq.i16 d16, d16, d17
332 # CHECK: vceq.i32 d16, d16, d17
333 # CHECK: vceq.f32 d16, d16, d17
334 # CHECK: vceq.i8 q8, q8, q9
335 # CHECK: vceq.i16 q8, q8, q9
336 # CHECK: vceq.i32 q8, q8, q9
337 # CHECK: vceq.f32 q8, q8, q9
430 # CHECK: vceq.i8 d16, d16, #0
/external/libjpeg-turbo/simd/
Djsimd_arm_neon.S2745 vceq.i16 q0, q0, q8
2746 vceq.i16 q1, q1, q8
2747 vceq.i16 q2, q2, q8
2748 vceq.i16 q3, q3, q8
2749 vceq.i16 q4, q4, q8
2750 vceq.i16 q5, q5, q8
2751 vceq.i16 q6, q6, q8
2752 vceq.i16 q7, q7, q8

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