/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | fdivs.ll | 13 ; VFP2: vdiv.f32 s0, s1, s0 16 ; NFP1: vdiv.f32 s0, s1, s0 18 ; NFP0: vdiv.f32 s0, s1, s0 21 ; CORTEXA8: vdiv.f32 s0, s1, s0 23 ; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
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D | vdiv_combine.ll | 11 ; CHECK-NOT: vdiv 27 ; CHECK-NOT: vdiv 41 ; CHECK: vdiv 55 ; CHECK: vdiv 69 ; CHECK-NOT: vdiv 83 ; CHECK-NOT: vdiv
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D | fparith.ll | 69 ;CHECK: vdiv.f32 77 ;CHECK: vdiv.f64
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/external/llvm/test/CodeGen/ARM/ |
D | fdivs.ll | 13 ; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}} 16 ; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}} 18 ; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}} 21 ; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}} 23 ; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
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D | vdiv_combine.ll | 11 ; CHECK-NOT: {{vdiv|vmul}} 27 ; CHECK-NOT: {{vdiv|vmul}} 41 ; CHECK: {{vdiv|vmul}} 55 ; CHECK: {{vdiv|vmul}} 69 ; CHECK-NOT: {{vdiv|vmul}} 83 ; CHECK-NOT: {{vdiv|vmul}}
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D | fparith.ll | 69 ;CHECK: vdiv.f32 77 ;CHECK: vdiv.f64
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/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
D | vdiv.ll | 1 ; Show that we know how to translate vdiv. 34 ; ASM-NEXT: vdiv.f32 s0, s0, s1 55 ; ASM-NEXT: vdiv.f64 d0, d0, d1
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D | div-vec.ll | 34 ; ASM: vdiv.f32 s12, s12, s13 36 ; ASM: vdiv.f32 s12, s12, s13 38 ; ASM: vdiv.f32 s12, s12, s13 40 ; ASM: vdiv.f32 s0, s0, s4 48 ; IASM-NOT: vdiv
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/external/capstone/suite/MC/ARM/ |
D | simple-fp-encoding.s.cs | 6 0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16 7 0x80,0x0a,0x80,0xee = vdiv.f32 s0, s1, s0 8 0xa3,0x2a,0xc2,0xee = vdiv.f32 s5, s5, s7 9 0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7
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/external/llvm/test/MC/ARM/ |
D | simple-fp-encoding.s | 13 vdiv.f64 d16, d17, d16 14 vdiv.f32 s0, s1, s0 15 vdiv.f32 s5, s7 16 vdiv.f64 d5, d7 18 @ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] 19 @ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] 20 @ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee] 21 @ CHECK: vdiv.f64 d5, d5, d7 @ encoding: [0x07,0x5b,0x85,0xee]
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D | fullfp16.s | 12 vdiv.f16 s0, s1, s0 13 @ ARM: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x80,0xee] 14 @ THUMB: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0xee,0x80,0x09]
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D | single-precision-fp.s | 7 vdiv.f64 d4, d5, d6 15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
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D | fullfp16-neg.s | 10 vdiv.f16 s0, s1, s0
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | simple-fp-encoding.s | 15 @ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee] 16 vdiv.f64 d16, d17, d16 18 @ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee] 19 vdiv.f32 s0, s1, s0
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/external/compiler-rt/lib/builtins/arm/ |
D | divsf3vfp.S | 23 vdiv.f32 s13, s14, s15
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D | divdf3vfp.S | 23 vdiv.f64 d5, d6, d7
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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
D | fp.arith.ll | 122 ; ARM32: vdiv.f32 s{{[0-9]+}}, s 135 ; ARM32: vdiv.f64 d{{[0-9]+}}, d
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | fp-encoding.txt | 16 # CHECK: vdiv.f64 d16, d17, d16 19 # CHECK: vdiv.f32 s0, s1, s0
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/external/llvm/test/MC/Disassembler/ARM/ |
D | fp-encoding.txt | 16 # CHECK: vdiv.f64 d16, d17, d16 19 # CHECK: vdiv.f32 s0, s1, s0
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D | fullfp16-thumb.txt | 9 # CHECK: vdiv.f16 s0, s1, s0
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D | fullfp16-arm.txt | 9 # CHECK: vdiv.f16 s0, s1, s0
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/external/llvm/test/CodeGen/Thumb2/ |
D | float-ops.ll | 67 ; HARD: vdiv.f32 s 77 ; DP: vdiv.f64 d0, d0, d1
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrVFP.td | 382 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 388 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 394 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm", 2241 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 2242 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
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/external/v8/src/arm/ |
D | assembler-arm.h | 1271 void vdiv(const DwVfpRegister dst, 1275 void vdiv(const SwVfpRegister dst, const SwVfpRegister src1,
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrVFP.td | 230 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 235 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
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