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/external/llvm/test/CodeGen/ARM/
Dvminmaxnm-safe.ll7 ; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
10 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
16 ; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
19 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
109 ; CHECK-NOT: vmaxnm.f32
117 ; CHECK-NOT: vmaxnm.f32
125 ; CHECK-NOT: vmaxnm.f32
133 ; CHECK-NOT: vmaxnm.f32
141 ; CHECK-NOT: vmaxnm.f32
149 ; CHECK-NOT: vmaxnm.f32
[all …]
Dvminmaxnm.ll80 ; CHECK: vmaxnm.f32
89 ; CHECK: vmaxnm.f32
98 ; CHECK: vmaxnm.f32
107 ; CHECK: vmaxnm.f32
116 ; CHECK: vmaxnm.f32
125 ; CHECK: vmaxnm.f32
134 ; CHECK: vmaxnm.f32
143 ; CHECK: vmaxnm.f64
241 ; CHECK: vmaxnm.f32
242 ; CHECK: vmaxnm.f32
[all …]
/external/llvm/test/MC/ARM/
Dneon-v8.s3 vmaxnm.f32 d4, d5, d1
4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x11,0x4f,0x05,0xf3]
5 vmaxnm.f32 q2, q4, q6
6 @ CHECK: vmaxnm.f32 q2, q4, q6 @ encoding: [0x5c,0x4f,0x08,0xf3]
Dthumb-neon-v8.s3 vmaxnm.f32 d4, d5, d1
4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x05,0xff,0x11,0x4f]
5 vmaxnm.f32 q2, q4, q6
6 @ CHECK: vmaxnm.f32 q2, q4, q6 @ encoding: [0x08,0xff,0x5c,0x4f]
Dfp-armv8.s83 vmaxnm.f32 s5, s12, s0
84 @ CHECK: vmaxnm.f32 s5, s12, s0 @ encoding: [0x00,0x2a,0xc6,0xfe]
85 vmaxnm.f64 d5, d22, d30
86 @ CHECK: vmaxnm.f64 d5, d22, d30 @ encoding: [0xae,0x5b,0x86,0xfe]
Dthumb-fp-armv8.s86 vmaxnm.f32 s5, s12, s0
87 @ CHECK: vmaxnm.f32 s5, s12, s0 @ encoding: [0xc6,0xfe,0x00,0x2a]
88 vmaxnm.f64 d5, d22, d30
89 @ CHECK: vmaxnm.f64 d5, d22, d30 @ encoding: [0x86,0xfe,0xae,0x5b]
Dinvalid-fp-armv8.s46 vmaxnm.f32 s0, d2, d1
50 vmaxnm.f32 s0, q3, q1
52 vmaxnm.f64 q0, s3, q1
Dinvalid-neon-v8.s3 vmaxnm.f32 s4, d5, q1
5 vmaxnm.f64.f64 s4, d5, q1
Ddirective-arch_extension-simd.s19 vmaxnm.f32 s0, s0, s0
24 vmaxnm.f64 d0, d0, d0
127 vmaxnm.f32 s0, s0, s0
132 vmaxnm.f64 d0, d0, d0
Dfullfp16-neon.s200 vmaxnm.f16 d0, d1, d2
201 vmaxnm.f16 q0, q1, q2
202 @ ARM: vmaxnm.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x11,0xf3]
203 @ ARM: vmaxnm.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x12,0xf3]
204 @ THUMB: vmaxnm.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0f]
205 @ THUMB: vmaxnm.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0f]
Ddirective-arch_extension-fp.s30 vmaxnm.f32 s0, s0, s0
43 vmaxnm.f64 d0, d0, d0
166 vmaxnm.f32 s0, s0, s0
179 vmaxnm.f64 d0, d0, d0
Dfullfp16.s161 vmaxnm.f16 s5, s12, s0
162 @ ARM: vmaxnm.f16 s5, s12, s0 @ encoding: [0x00,0x29,0xc6,0xfe]
163 @ THUMB: vmaxnm.f16 s5, s12, s0 @ encoding: [0xc6,0xfe,0x00,0x29]
Dfullfp16-neon-neg.s146 vmaxnm.f16 d0, d1, d2
147 vmaxnm.f16 q0, q1, q2
Dfullfp16-neg.s119 vmaxnm.f16 s5, s12, s0
/external/capstone/suite/MC/ARM/
Dneon-v8.s.cs2 0x11,0x4f,0x05,0xf3 = vmaxnm.f32 d4, d5, d1
3 0x5c,0x4f,0x08,0xf3 = vmaxnm.f32 q2, q4, q6
Dthumb-neon-v8.s.cs2 0x05,0xff,0x11,0x4f = vmaxnm.f32 d4, d5, d1
3 0x08,0xff,0x5c,0x4f = vmaxnm.f32 q2, q4, q6
Dfp-armv8.s.cs34 0x00,0x2a,0xc6,0xfe = vmaxnm.f32 s5, s12, s0
35 0xae,0x5b,0x86,0xfe = vmaxnm.f64 d5, d22, d30
Dthumb-fp-armv8.s.cs34 0xc6,0xfe,0x00,0x2a = vmaxnm.f32 s5, s12, s0
35 0x86,0xfe,0xae,0x5b = vmaxnm.f64 d5, d22, d30
/external/llvm/test/MC/Disassembler/ARM/
Dthumb-neon-v8.txt4 # CHECK: vmaxnm.f32 d4, d5, d1
6 # CHECK: vmaxnm.f32 q2, q4, q6
Dneon-v8.txt4 # CHECK: vmaxnm.f32 d4, d5, d1
6 # CHECK: vmaxnm.f32 q2, q4, q6
Dthumb-fp-armv8.txt107 # CHECK: vmaxnm.f32 s5, s12, s0
110 # CHECK: vmaxnm.f64 d5, d22, d30
Dfp-armv8.txt103 # CHECK: vmaxnm.f32 s5, s12, s0
106 # CHECK: vmaxnm.f64 d5, d22, d30
Dfullfp16-neon-arm.txt124 # CHECK: vmaxnm.f16 d0, d1, d2
125 # CHECK: vmaxnm.f16 q0, q1, q2
Dfullfp16-neon-thumb.txt124 # CHECK: vmaxnm.f16 d0, d1, d2
125 # CHECK: vmaxnm.f16 q0, q1, q2
Dfullfp16-thumb.txt118 # CHECK: vmaxnm.f16 s5, s12, s0

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