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Searched refs:vmls (Results 1 – 25 of 57) sorted by relevance

123

/external/llvm/test/MC/ARM/
Dneon-mul-accum-encoding.s54 vmls.i8 d16, d18, d17
55 vmls.i16 d16, d18, d17
56 vmls.i32 d16, d18, d17
57 vmls.f32 d16, d18, d17
58 vmls.i8 q9, q8, q10
59 vmls.i16 q9, q8, q10
60 vmls.i32 q9, q8, q10
61 vmls.f32 q9, q8, q10
62 vmls.i16 q4, q12, d6[2]
64 @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3]
[all …]
Dneont2-mul-accum-encoding.s58 vmls.i8 d16, d18, d17
59 vmls.i16 d16, d18, d17
60 vmls.i32 d16, d18, d17
61 vmls.f32 d16, d18, d17
62 vmls.i8 q9, q8, q10
63 vmls.i16 q9, q8, q10
64 vmls.i32 q9, q8, q10
65 vmls.f32 q9, q8, q10
66 vmls.i16 q4, q12, d6[2]
68 @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0x42,0xff,0xa1,0x09]
[all …]
Dfullfp16-neon.s46 vmls.f16 d0, d1, d2
47 vmls.f16 q0, q1, q2
48 @ ARM: vmls.f16 d0, d1, d2 @ encoding: [0x12,0x0d,0x31,0xf2]
49 @ ARM: vmls.f16 q0, q1, q2 @ encoding: [0x54,0x0d,0x32,0xf2]
50 @ THUMB: vmls.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x12,0x0d]
51 @ THUMB: vmls.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x0d]
53 vmls.f16 d5, d6, d7[2]
54 vmls.f16 q5, q6, d7[3]
55 @ ARM: vmls.f16 d5, d6, d7[2] @ encoding: [0x67,0x55,0x96,0xf2]
56 @ ARM: vmls.f16 q5, q6, d7[3] @ encoding: [0x6f,0xa5,0x9c,0xf3]
[all …]
Dfullfp16-neon-neg.s36 vmls.f16 d0, d1, d2
37 vmls.f16 q0, q1, q2
41 vmls.f16 d5, d6, d7[2]
42 vmls.f16 q5, q6, d7[3]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-mul-accum-encoding.s46 vmls.i8 d16, d18, d17
47 vmls.i16 d16, d18, d17
48 vmls.i32 d16, d18, d17
49 vmls.f32 d16, d18, d17
50 vmls.i8 q9, q8, q10
51 vmls.i16 q9, q8, q10
52 vmls.i32 q9, q8, q10
53 vmls.f32 q9, q8, q10
55 @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0x42,0xff,0xa1,0x09]
56 @ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0x52,0xff,0xa1,0x09]
[all …]
Dneon-mul-accum-encoding.s35 @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3]
36 vmls.i8 d16, d18, d17
37 @ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3]
38 vmls.i16 d16, d18, d17
39 @ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3]
40 vmls.i32 d16, d18, d17
41 @ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2]
42 vmls.f32 d16, d18, d17
43 @ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3]
44 vmls.i8 q9, q8, q10
[all …]
Dneon-mul-encoding.s44 vmls.i8 d16, d18, d17
45 vmls.i16 d16, d18, d17
46 vmls.i32 d16, d18, d17
47 vmls.f32 d16, d18, d17
48 vmls.i8 q9, q8, q10
49 vmls.i16 q9, q8, q10
50 vmls.i32 q9, q8, q10
51 vmls.f32 q9, q8, q10
53 @ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3]
54 @ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3]
[all …]
Dsimple-fp-encoding.s99 @ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
100 vmls.f64 d16, d18, d17
102 @ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]
103 vmls.f32 s1, s2, s0
/external/capstone/suite/MC/ARM/
Dneon-mul-accum-encoding.s.cs23 0xa1,0x09,0x42,0xf3 = vmls.i8 d16, d18, d17
24 0xa1,0x09,0x52,0xf3 = vmls.i16 d16, d18, d17
25 0xa1,0x09,0x62,0xf3 = vmls.i32 d16, d18, d17
26 0xb1,0x0d,0x62,0xf2 = vmls.f32 d16, d18, d17
27 0xe4,0x29,0x40,0xf3 = vmls.i8 q9, q8, q10
28 0xe4,0x29,0x50,0xf3 = vmls.i16 q9, q8, q10
29 0xe4,0x29,0x60,0xf3 = vmls.i32 q9, q8, q10
30 0xf4,0x2d,0x60,0xf2 = vmls.f32 q9, q8, q10
31 0xe6,0x84,0x98,0xf3 = vmls.i16 q4, q12, d6[2]
Dneont2-mul-accum-encoding.s.cs24 0x42,0xff,0xa1,0x09 = vmls.i8 d16, d18, d17
25 0x52,0xff,0xa1,0x09 = vmls.i16 d16, d18, d17
26 0x62,0xff,0xa1,0x09 = vmls.i32 d16, d18, d17
27 0x62,0xef,0xb1,0x0d = vmls.f32 d16, d18, d17
28 0x40,0xff,0xe4,0x29 = vmls.i8 q9, q8, q10
29 0x50,0xff,0xe4,0x29 = vmls.i16 q9, q8, q10
30 0x60,0xff,0xe4,0x29 = vmls.i32 q9, q8, q10
31 0x60,0xef,0xf4,0x2d = vmls.f32 q9, q8, q10
32 0x98,0xff,0xe6,0x84 = vmls.i16 q4, q12, d6[2]
/external/libavc/common/arm/
Dih264_inter_pred_filters_luma_vert_a9q.s138 vmls.u16 q7, q8, q12 @ temp -= temp2 * 5
142 vmls.u16 q10, q13, q12 @ temp4 -= temp5 * 5
149 vmls.u16 q8, q9, q12
157 vmls.u16 q7, q13, q12
163 vmls.u16 q9, q10, q12
171 vmls.u16 q8, q13, q12
178 vmls.u16 q7, q10, q12
181 vmls.u16 q9, q13, q12
218 vmls.u16 q4, q5, q12 @ temp -= temp2 * 5
224 vmls.u16 q8, q9, q12
[all …]
Dih264_inter_pred_luma_vert_qpel_a9q.s145 vmls.u16 q7, q8, q12 @ temp -= temp2 * 5
149 vmls.u16 q10, q13, q12 @ temp4 -= temp5 * 5
156 vmls.u16 q8, q9, q12
166 vmls.u16 q7, q13, q12
172 vmls.u16 q9, q10, q12
182 vmls.u16 q8, q13, q12
189 vmls.u16 q7, q10, q12
192 vmls.u16 q9, q13, q12
233 vmls.u16 q4, q5, q12 @ temp -= temp2 * 5
239 vmls.u16 q8, q9, q12
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_qpel_a9q.s163 vmls.u16 q3, q4, q12
177 vmls.u16 q4, q5, q12
191 vmls.u16 q5, q6, q12
205 vmls.u16 q6, q7, q12
219 vmls.u16 q7, q8, q12
236 vmls.u16 q8, q9, q12
266 vmls.u16 q10, q1, q12
305 vmls.u16 q4, q1, q12
341 vmls.u16 q14, q1, q12
391 vmls.u16 q3, q4, q12
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_hpel_a9q.s149 vmls.s16 q12, q11, d1[0] @ temp -= temp2 * 5
154 vmls.s16 q13, q10, d1[0] @ temp -= temp2 * 5
158 vmls.s16 q14, q10, d1[0] @ temp -= temp2 * 5
209 vmls.s16 q12, q11, d1[0] @ temp -= temp2 * 5
214 vmls.s16 q13, q10, d1[0] @ temp -= temp2 * 5
217 vmls.s16 q14, q10, d1[0] @ temp -= temp2 * 5
282 vmls.s16 q12, q11, d1[0] @ temp -= temp2 * 5
285 vmls.s16 q13, q15, d1[0] @ temp -= temp2 * 5
314 vmls.s16 q12, q11, d1[0] @ temp -= temp2 * 5
317 vmls.s16 q13, q15, d1[0] @ temp -= temp2 * 5
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_hpel_a9q.s176 vmls.u16 q9, q11, q15
178 vmls.u16 q10, q13, q15
181 vmls.u16 q11, q13, q15
253 vmls.u16 q9, q11, q15
255 vmls.u16 q10, q13, q15
258 vmls.u16 q11, q13, q15
337 vmls.u16 q6, q8, q12
340 vmls.u16 q7, q11, q12
350 vmls.u16 q14, q9, q12
367 vmls.u16 q7, q8, q12
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dfnmacs.ll8 ; VFP2: vmls.f32
11 ; NEON: vmls.f32
24 ; VFP2: vmls.f64
27 ; NEON: vmls.f64
Dvmls.ll5 ;CHECK: vmls.i8
16 ;CHECK: vmls.i16
27 ;CHECK: vmls.i32
38 ;CHECK: vmls.f32
49 ;CHECK: vmls.i8
60 ;CHECK: vmls.i16
71 ;CHECK: vmls.i32
82 ;CHECK: vmls.f32
/external/llvm/test/CodeGen/ARM/
Dfnmacs.ll8 ; VFP2: vmls.f32
11 ; NEON: vmls.f32
24 ; VFP2: vmls.f64
27 ; NEON: vmls.f64
Dvmls.ll5 ;CHECK: vmls.i8
16 ;CHECK: vmls.i16
27 ;CHECK: vmls.i32
38 ;CHECK: vmls.f32
49 ;CHECK: vmls.i8
60 ;CHECK: vmls.i16
71 ;CHECK: vmls.i32
82 ;CHECK: vmls.f32
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Dvmls.ll1 ; Show that we can take advantage of the vmls instruction for floating point
37 ; ASM: vmls.f32 s21, s20, s22
39 ; IASM-NOT: vmls.f32
51 ; ASM: vmls.f64 d21, d20, d22
53 ; IASM-NOT: vmls.f64
/external/arm-neon-tests/
Dref_vmls_n.c26 #define INSN_NAME vmls
Dref_vmls.c26 #define INSN_NAME vmls
Dref_vmls_lane.c26 #define INSN_NAME vmls
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-arm.txt34 # CHECK: vmls.f16 d0, d1, d2
35 # CHECK: vmls.f16 q0, q1, q2
39 # CHECK: vmls.f16 d5, d6, d7[2]
40 # CHECK: vmls.f16 q5, q6, d7[3]
Dfullfp16-neon-thumb.txt34 # CHECK: vmls.f16 d0, d1, d2
35 # CHECK: vmls.f16 q0, q1, q2
39 # CHECK: vmls.f16 d5, d6, d7[2]
40 # CHECK: vmls.f16 q5, q6, d7[3]

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