/external/llvm/test/CodeGen/AArch64/ |
D | arm64-ldp-cluster.ll | 9 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui 10 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui 14 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui 15 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui 29 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui 30 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui 34 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui 35 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui 50 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDURWi 51 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDURWi [all …]
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D | tailcall_misched_graph.ll | 29 ; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1> 30 ; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2> 31 ; CHECK: STRXui %vreg{{.*}}, <fi#-4> 43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4> 44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>
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D | arm64-fast-isel-rem.ll | 7 ; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr 9 ; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | RegAllocPBQP.h | 54 void recordVReg(unsigned vreg, PBQP::Graph::NodeItr node, in recordVReg() argument 57 assert(vreg2Node.find(vreg) == vreg2Node.end() && "Re-mapping vreg."); in recordVReg() 58 assert(allowedSets[vreg].empty() && "vreg already has pregs."); in recordVReg() 60 node2VReg[node] = vreg; in recordVReg() 61 vreg2Node[vreg] = node; in recordVReg() 62 std::copy(arBegin, arEnd, std::back_inserter(allowedSets[vreg])); in recordVReg() 69 PBQP::Graph::NodeItr getNodeForVReg(unsigned vreg) const; 73 bool isPRegOption(unsigned vreg, unsigned option) const { in isPRegOption() argument 76 return !isSpillOption(vreg, option); in isPRegOption() 81 bool isSpillOption(unsigned vreg, unsigned option) const { in isSpillOption() argument [all …]
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D | MachineRegisterInfo.h | 301 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 302 LiveIns.push_back(std::make_pair(Reg, vreg));
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/external/valgrind/VEX/priv/ |
D | host_generic_reg_alloc2.c | 119 HReg vreg; member 181 if (HRegUsage__contains(®_usages_in[m], state[k].vreg)) in findMostDistantlyMentionedVReg() 195 static void sanity_check_spill_offset ( VRegLR* vreg ) in sanity_check_spill_offset() argument 197 switch (vreg->reg_class) { in sanity_check_spill_offset() 199 vassert(0 == ((UShort)vreg->spill_offset % 16)); break; in sanity_check_spill_offset() 201 vassert(0 == ((UShort)vreg->spill_offset % 8)); break; in sanity_check_spill_offset() 483 (*ppReg)(rreg_state[z].vreg); \ in doRegisterAllocation() 523 rreg_state[j].vreg = INVALID_HREG; in doRegisterAllocation() 604 HReg vreg = reg_usage_arr[ii].vRegs[j]; in doRegisterAllocation() local 605 vassert(hregIsVirtual(vreg)); in doRegisterAllocation() [all …]
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/external/v8/src/compiler/ |
D | live-range-separator.cc | 50 DCHECK_NULL(data->live_ranges()[splinter->vreg()]); in CreateSplinter() 51 data->live_ranges()[splinter->vreg()] = splinter; in CreateSplinter() 55 TRACE("creating splinter for range %d between %d and %d\n", range->vreg(), in CreateSplinter() 124 for (size_t vreg = 0; vreg < virt_reg_count; ++vreg) { in Splinter() local 125 TopLevelLiveRange *range = data()->live_ranges()[vreg]; in Splinter() 171 int to_remove = range->vreg(); in Merge()
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D | register-allocator.cc | 836 TopLevelLiveRange::TopLevelLiveRange(int vreg, MachineRepresentation rep) in TopLevelLiveRange() argument 838 vreg_(vreg), in TopLevelLiveRange() 854 return IsSplinter() ? splintered_from()->vreg() : vreg(); in debug_virt_reg() 1096 TRACE("Shorten live range %d to [%d\n", vreg(), start.value()); in ShortenTo() 1106 TRACE("Ensure live range %d in interval [%d %d[\n", vreg(), start.value(), in EnsureInterval() 1127 TRACE("Add to live range %d interval [%d %d[\n", vreg(), start.value(), in AddUseInterval() 1154 TRACE("Add to live range %d use position %d\n", vreg(), pos.value()); in AddUsePosition() 1200 os << "Range: " << range->TopLevel()->vreg() << ":" << range->relative_id() in operator <<() 1322 os << range->vreg() << " "; in Print() 1434 int vreg = virtual_register_count_++; in GetNextLiveRangeId() local [all …]
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D | register-allocator-verifier.cc | 162 int vreg = unallocated->virtual_register(); in BuildConstraint() local 163 constraint->virtual_register_ = vreg; in BuildConstraint() 171 if (sequence()->IsFP(vreg)) { in BuildConstraint() 191 if (sequence()->IsFP(vreg)) { in BuildConstraint() 200 ElementSizeLog2Of(sequence()->GetRepresentation(vreg)); in BuildConstraint() 563 int vreg = pair.second; in VerifyGapMoves() local 570 vreg); in VerifyGapMoves() 576 pending, vreg); in VerifyGapMoves() 578 new (zone()) FinalAssessment(vreg, pending); in VerifyGapMoves()
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D | instruction-selector-impl.h | 187 InstructionOperand DefineSameAsFirstForVreg(int vreg) { in DefineSameAsFirstForVreg() argument 188 return UnallocatedOperand(UnallocatedOperand::SAME_AS_FIRST_INPUT, vreg); in DefineSameAsFirstForVreg() 191 InstructionOperand DefineAsRegistertForVreg(int vreg) { in DefineAsRegistertForVreg() argument 192 return UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg); in DefineAsRegistertForVreg() 195 InstructionOperand UseRegisterForVreg(int vreg) { in UseRegisterForVreg() argument 197 UnallocatedOperand::USED_AT_START, vreg); in UseRegisterForVreg()
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D | register-allocator-verifier.h | 215 void AddDelayedAssessment(InstructionOperand op, int vreg) { in AddDelayedAssessment() argument 218 map_.insert(std::make_pair(op, vreg)); in AddDelayedAssessment() 220 CHECK_EQ(it->second, vreg); in AddDelayedAssessment()
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D | graph-visualizer.cc | 280 void PrintLiveRange(const LiveRange* range, const char* type, int vreg); 573 int vreg = range->vreg(); in PrintLiveRangeChain() local 576 PrintLiveRange(child, type, vreg); in PrintLiveRangeChain() 581 int vreg) { in PrintLiveRange() argument 584 os_ << vreg << ":" << range->relative_id() << " " << type; in PrintLiveRange() 618 os_ << " " << vreg; in PrintLiveRange()
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D | instruction-scheduler.cc | 176 int32_t vreg = UnallocatedOperand::cast(input)->virtual_register(); in AddInstruction() local 177 auto it = operands_map_.find(vreg); in AddInstruction()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | RegAllocPBQP.cpp | 169 PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const { in getNodeForVReg() 170 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg); in getNodeForVReg() 177 PBQPRAProblem::getAllowedSet(unsigned vreg) const { in getAllowedSet() 178 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg); in getAllowedSet() 184 unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const { in getPRegForOption() argument 185 assert(isPRegOption(vreg, option) && "Not a preg option."); in getPRegForOption() 187 const AllowedSet& allowedSet = getAllowedSet(vreg); in getPRegForOption() 220 unsigned vreg = *vregItr; in build() local 221 const TargetRegisterClass *trc = mri->getRegClass(vreg); in build() 222 const LiveInterval *vregLI = &lis->getInterval(vreg); in build() [all …]
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/external/mesa3d/src/gallium/drivers/r600/sb/ |
D | sb_bc_finalize.cpp | 486 unsigned vreg = v->gpr.sel(); in copy_fetch_src() local 490 reg = vreg; in copy_fetch_src() 491 else if ((unsigned)reg != vreg) { in copy_fetch_src() 591 unsigned vreg = v->gpr.sel(); in finalize_fetch() local 595 reg = vreg; in finalize_fetch() 596 else if ((unsigned)reg != vreg) { in finalize_fetch() 638 unsigned vreg = v->gpr.sel(); in finalize_fetch() local 642 reg = vreg; in finalize_fetch() 643 else if ((unsigned)reg != vreg) { in finalize_fetch() 710 unsigned vreg = v->gpr.sel(); in finalize_cf() local [all …]
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/external/v8/src/x64/ |
D | assembler-x64-inl.h | 228 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument 234 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix() 237 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix() 242 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, in emit_vex_prefix() argument 246 XMMRegister ivreg = {vreg.code()}; in emit_vex_prefix() 252 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument 258 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix() 261 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix() 266 void Assembler::emit_vex_prefix(Register reg, Register vreg, const Operand& rm, in emit_vex_prefix() argument 270 XMMRegister ivreg = {vreg.code()}; in emit_vex_prefix()
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D | assembler-x64.cc | 4153 void Assembler::bmi1q(byte op, Register reg, Register vreg, Register rm) { in bmi1q() argument 4156 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1); in bmi1q() 4162 void Assembler::bmi1q(byte op, Register reg, Register vreg, const Operand& rm) { in bmi1q() argument 4165 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW1); in bmi1q() 4171 void Assembler::bmi1l(byte op, Register reg, Register vreg, Register rm) { in bmi1l() argument 4174 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0); in bmi1l() 4180 void Assembler::bmi1l(byte op, Register reg, Register vreg, const Operand& rm) { in bmi1l() argument 4183 emit_vex_prefix(reg, vreg, rm, kLZ, kNone, k0F38, kW0); in bmi1l() 4321 void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, in bmi2q() argument 4325 emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW1); in bmi2q() [all …]
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/external/llvm/test/CodeGen/ARM/ |
D | misched-copy-arm.ll | 36 ; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1> 37 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]] 38 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
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D | fast-isel-shift-materialize.ll | 6 ; When materializing the '2' for the shifts below, the second shift kills the vreg 7 ; we materialize in to. However, the first shift was also killing that vreg.
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D | fast-isel-remat-same-constant.ll | 7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou… 9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
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D | fast-isel-update-valuemap-for-extract.ll | 6 ; This test ensures that when fast-isel rewrites uses of the vreg for %tmp29, it also
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/external/llvm/test/CodeGen/PowerPC/ |
D | quadint-return.ll | 17 ; CHECK: %X3<def> = COPY %vreg 18 ; CHECK-NEXT: %X4<def> = COPY %vreg
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/external/vixl/test/aarch64/ |
D | test-utils-aarch64.cc | 160 const VRegister& vreg) { in Equal128() argument 161 VIXL_ASSERT(vreg.Is128Bits()); in Equal128() 163 vec128_t result = core->qreg(vreg.GetCode()); in Equal128() 207 const VRegister& vreg) { in Equal64() argument 208 VIXL_ASSERT(vreg.Is64Bits()); in Equal64() 209 uint64_t result = core->dreg_bits(vreg.GetCode()); in Equal64()
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/external/llvm/test/CodeGen/AMDGPU/ |
D | rename-independent-subregs.mir | 8 # in combination with sub0 and needs to stay with the original vreg.
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/external/v8/src/ia32/ |
D | assembler-ia32.cc | 2807 void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) { in bmi1() argument 2810 emit_vex_prefix(vreg, kLZ, kNone, k0F38, kW0); in bmi1() 2846 void Assembler::bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg, in bmi2() argument 2850 emit_vex_prefix(vreg, kLZ, pp, k0F38, kW0); in bmi2() 2859 Register vreg = {0}; // VEX.vvvv unused in rorx() local 2861 emit_vex_prefix(vreg, kLZ, kF2, k0F3A, kW0); in rorx() 2889 void Assembler::emit_vex_prefix(XMMRegister vreg, VectorLength l, SIMDPrefix pp, in emit_vex_prefix() argument 2895 EMIT(w | ((~vreg.code() & 0xf) << 3) | l | pp); in emit_vex_prefix() 2898 EMIT(((~vreg.code()) << 3) | l | pp); in emit_vex_prefix() 2903 void Assembler::emit_vex_prefix(Register vreg, VectorLength l, SIMDPrefix pp, in emit_vex_prefix() argument [all …]
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