• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1  /*
2    This software is available to you under a choice of one of two
3    licenses.  You may choose to be licensed under the terms of the GNU
4    General Public License (GPL) Version 2, available at
5    <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
6    license, available in the LICENSE.TXT file accompanying this
7    software.  These details are also available at
8    <http://openib.org/license.html>.
9  
10    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13    NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14    BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15    ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16    CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17    SOFTWARE.
18  
19    Copyright (c) 2004 Mellanox Technologies Ltd.  All rights reserved.
20  */
21  
22  FILE_LICENCE ( GPL2_ONLY );
23  
24  /***
25   *** This file was generated at "Tue Nov 22 15:21:23 2005"
26   *** by:
27   ***    % csp_bf -copyright=/mswg/misc/license-header.txt -prefix arbelprm_ -bits -fixnames MT25218_PRM.csp
28   ***/
29  
30  #ifndef H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
31  #define H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
32  
33  /* UD Address Vector */
34  
35  struct arbelprm_ud_address_vector_st {	/* Little Endian */
36      pseudo_bit_t	pd[0x00018];           /* Protection Domain */
37      pseudo_bit_t	port_number[0x00002];  /* Port number
38                                                   1 - Port 1
39                                                   2 - Port 2
40                                                   other - reserved */
41      pseudo_bit_t	reserved0[0x00006];
42  /* -------------- */
43      pseudo_bit_t	rlid[0x00010];         /* Remote (Destination) LID */
44      pseudo_bit_t	my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
45      pseudo_bit_t	g[0x00001];            /* Global address enable - if set, GRH will be formed for packet header */
46      pseudo_bit_t	reserved1[0x00008];
47  /* -------------- */
48      pseudo_bit_t	hop_limit[0x00008];    /* IPv6 hop limit */
49      pseudo_bit_t	max_stat_rate[0x00003];/* Maximum static rate control.
50                                                   0 - 4X injection rate
51                                                   1 - 1X injection rate
52                                                   other - reserved
53                                                    */
54      pseudo_bit_t	reserved2[0x00001];
55      pseudo_bit_t	msg[0x00002];          /* Max Message size, size is 256*2^MSG bytes */
56      pseudo_bit_t	reserved3[0x00002];
57      pseudo_bit_t	mgid_index[0x00006];   /* Index to port GID table
58                                                   mgid_index = (port_number-1) * 2^log_max_gid + gid_index
59                                                   Where:
60                                                   1. log_max_gid is taken from QUERY_DEV_LIM command
61                                                   2. gid_index is the index to the GID table */
62      pseudo_bit_t	reserved4[0x0000a];
63  /* -------------- */
64      pseudo_bit_t	flow_label[0x00014];   /* IPv6 flow label */
65      pseudo_bit_t	tclass[0x00008];       /* IPv6 TClass */
66      pseudo_bit_t	sl[0x00004];           /* InfiniBand Service Level (SL) */
67  /* -------------- */
68      pseudo_bit_t	rgid_127_96[0x00020];  /* Remote GID[127:96] */
69  /* -------------- */
70      pseudo_bit_t	rgid_95_64[0x00020];   /* Remote GID[95:64] */
71  /* -------------- */
72      pseudo_bit_t	rgid_63_32[0x00020];   /* Remote GID[63:32] */
73  /* -------------- */
74      pseudo_bit_t	rgid_31_0[0x00020];    /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
75  /* -------------- */
76  };
77  
78  /* Send doorbell */
79  
80  struct arbelprm_send_doorbell_st {	/* Little Endian */
81      pseudo_bit_t	nopcode[0x00005];      /* Opcode of descriptor to be executed */
82      pseudo_bit_t	f[0x00001];            /* Fence bit. If set, descriptor is fenced */
83      pseudo_bit_t	reserved0[0x00002];
84      pseudo_bit_t	wqe_counter[0x00010];  /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
85      pseudo_bit_t	wqe_cnt[0x00008];      /* Number of WQEs posted with this doorbell. Must be grater then zero. */
86  /* -------------- */
87      pseudo_bit_t	nds[0x00006];          /* Next descriptor size (in 16-byte chunks) */
88      pseudo_bit_t	reserved1[0x00002];
89      pseudo_bit_t	qpn[0x00018];          /* QP number this doorbell is rung on */
90  /* -------------- */
91  };
92  
93  /* ACCESS_LAM_inject_errors_input_modifier */
94  
95  struct arbelprm_access_lam_inject_errors_input_modifier_st {	/* Little Endian */
96      pseudo_bit_t	index3[0x00007];
97      pseudo_bit_t	q3[0x00001];
98      pseudo_bit_t	index2[0x00007];
99      pseudo_bit_t	q2[0x00001];
100      pseudo_bit_t	index1[0x00007];
101      pseudo_bit_t	q1[0x00001];
102      pseudo_bit_t	index0[0x00007];
103      pseudo_bit_t	q0[0x00001];
104  /* -------------- */
105  };
106  
107  /* ACCESS_LAM_inject_errors_input_parameter */
108  
109  struct arbelprm_access_lam_inject_errors_input_parameter_st {	/* Little Endian */
110      pseudo_bit_t	ba[0x00002];           /* Bank Address */
111      pseudo_bit_t	da[0x00002];           /* Dimm Address */
112      pseudo_bit_t	reserved0[0x0001c];
113  /* -------------- */
114      pseudo_bit_t	ra[0x00010];           /* Row Address */
115      pseudo_bit_t	ca[0x00010];           /* Column Address */
116  /* -------------- */
117  };
118  
119  /*  */
120  
121  struct arbelprm_recv_wqe_segment_next_st {	/* Little Endian */
122      pseudo_bit_t	reserved0[0x00006];
123      pseudo_bit_t	nda_31_6[0x0001a];     /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
124  /* -------------- */
125      pseudo_bit_t	nds[0x00006];          /* Next WQE size in OctoWords (16 bytes).
126                                                   Zero value in NDS field signals end of WQEs? chain.
127                                                    */
128      pseudo_bit_t	reserved1[0x0001a];
129  /* -------------- */
130  };
131  
132  /* Send wqe segment data inline */
133  
134  struct arbelprm_wqe_segment_data_inline_st {	/* Little Endian */
135      pseudo_bit_t	byte_count[0x0000a];   /* Not including padding for 16Byte chunks */
136      pseudo_bit_t	reserved0[0x00015];
137      pseudo_bit_t	always1[0x00001];
138  /* -------------- */
139      pseudo_bit_t	data[0x00018];         /* Data may be more this segment size - in 16Byte chunks */
140      pseudo_bit_t	reserved1[0x00008];
141  /* -------------- */
142      pseudo_bit_t	reserved2[0x00040];
143  /* -------------- */
144  };
145  
146  /* Send wqe segment data ptr */
147  
148  struct arbelprm_wqe_segment_data_ptr_st {	/* Little Endian */
149      pseudo_bit_t	byte_count[0x0001f];
150      pseudo_bit_t	always0[0x00001];
151  /* -------------- */
152      pseudo_bit_t	l_key[0x00020];
153  /* -------------- */
154      pseudo_bit_t	local_address_h[0x00020];
155  /* -------------- */
156      pseudo_bit_t	local_address_l[0x00020];
157  /* -------------- */
158  };
159  
160  /* Send wqe segment rd */
161  
162  struct arbelprm_local_invalidate_segment_st {	/* Little Endian */
163      pseudo_bit_t	reserved0[0x00040];
164  /* -------------- */
165      pseudo_bit_t	mem_key[0x00018];
166      pseudo_bit_t	reserved1[0x00008];
167  /* -------------- */
168      pseudo_bit_t	reserved2[0x000a0];
169  /* -------------- */
170  };
171  
172  /* Fast_Registration_Segment */
173  
174  struct arbelprm_fast_registration_segment_st {	/* Little Endian */
175      pseudo_bit_t	reserved0[0x0001b];
176      pseudo_bit_t	lr[0x00001];           /* If set - Local Read access will be enabled */
177      pseudo_bit_t	lw[0x00001];           /* If set - Local Write access will be enabled */
178      pseudo_bit_t	rr[0x00001];           /* If set - Remote Read access will be enabled */
179      pseudo_bit_t	rw[0x00001];           /* If set - Remote Write access will be enabled */
180      pseudo_bit_t	a[0x00001];            /* If set - Remote Atomic access will be enabled */
181  /* -------------- */
182      pseudo_bit_t	pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list */
183  /* -------------- */
184      pseudo_bit_t	mem_key[0x00020];      /* Memory Key on which the fast registration is executed on. */
185  /* -------------- */
186      pseudo_bit_t	page_size[0x00005];    /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
187                                                   page_size should be less than 20. */
188      pseudo_bit_t	reserved1[0x00002];
189      pseudo_bit_t	zb[0x00001];           /* Zero Based Region */
190      pseudo_bit_t	pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list */
191  /* -------------- */
192      pseudo_bit_t	start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
193  /* -------------- */
194      pseudo_bit_t	start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
195  /* -------------- */
196      pseudo_bit_t	reg_len_h[0x00020];    /* Region Length[63:32] */
197  /* -------------- */
198      pseudo_bit_t	reg_len_l[0x00020];    /* Region Length[31:0] */
199  /* -------------- */
200  };
201  
202  /* Send wqe segment atomic */
203  
204  struct arbelprm_wqe_segment_atomic_st {	/* Little Endian */
205      pseudo_bit_t	swap_add_h[0x00020];
206  /* -------------- */
207      pseudo_bit_t	swap_add_l[0x00020];
208  /* -------------- */
209      pseudo_bit_t	compare_h[0x00020];
210  /* -------------- */
211      pseudo_bit_t	compare_l[0x00020];
212  /* -------------- */
213  };
214  
215  /* Send wqe segment remote address */
216  
217  struct arbelprm_wqe_segment_remote_address_st {	/* Little Endian */
218      pseudo_bit_t	remote_virt_addr_h[0x00020];
219  /* -------------- */
220      pseudo_bit_t	remote_virt_addr_l[0x00020];
221  /* -------------- */
222      pseudo_bit_t	rkey[0x00020];
223  /* -------------- */
224      pseudo_bit_t	reserved0[0x00020];
225  /* -------------- */
226  };
227  
228  /* end wqe segment bind */
229  
230  struct arbelprm_wqe_segment_bind_st {	/* Little Endian */
231      pseudo_bit_t	reserved0[0x0001d];
232      pseudo_bit_t	rr[0x00001];           /* If set, Remote Read Enable for bound window. */
233      pseudo_bit_t	rw[0x00001];           /* If set, Remote Write Enable for bound window.
234                                                    */
235      pseudo_bit_t	a[0x00001];            /* If set, Atomic Enable for bound window. */
236  /* -------------- */
237      pseudo_bit_t	reserved1[0x0001e];
238      pseudo_bit_t	zb[0x00001];           /* If set, Window is Zero Based. */
239      pseudo_bit_t	type[0x00001];         /* Window type.
240                                                   0 - Type one window
241                                                   1 - Type two window
242                                                    */
243  /* -------------- */
244      pseudo_bit_t	new_rkey[0x00020];     /* The new RKey of window to bind */
245  /* -------------- */
246      pseudo_bit_t	region_lkey[0x00020];  /* Local key of region, which window will be bound to */
247  /* -------------- */
248      pseudo_bit_t	start_address_h[0x00020];
249  /* -------------- */
250      pseudo_bit_t	start_address_l[0x00020];
251  /* -------------- */
252      pseudo_bit_t	length_h[0x00020];
253  /* -------------- */
254      pseudo_bit_t	length_l[0x00020];
255  /* -------------- */
256  };
257  
258  /* Send wqe segment ud */
259  
260  struct arbelprm_wqe_segment_ud_st {	/* Little Endian */
261      struct arbelprm_ud_address_vector_st	ud_address_vector;/* UD Address Vector */
262  /* -------------- */
263      pseudo_bit_t	destination_qp[0x00018];
264      pseudo_bit_t	reserved0[0x00008];
265  /* -------------- */
266      pseudo_bit_t	q_key[0x00020];
267  /* -------------- */
268      pseudo_bit_t	reserved1[0x00040];
269  /* -------------- */
270  };
271  
272  /* Send wqe segment rd */
273  
274  struct arbelprm_wqe_segment_rd_st {	/* Little Endian */
275      pseudo_bit_t	destination_qp[0x00018];
276      pseudo_bit_t	reserved0[0x00008];
277  /* -------------- */
278      pseudo_bit_t	q_key[0x00020];
279  /* -------------- */
280      pseudo_bit_t	reserved1[0x00040];
281  /* -------------- */
282  };
283  
284  /* Send wqe segment ctrl */
285  
286  struct arbelprm_wqe_segment_ctrl_send_st {	/* Little Endian */
287      pseudo_bit_t	always1[0x00001];
288      pseudo_bit_t	s[0x00001];            /* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */
289      pseudo_bit_t	e[0x00001];            /* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */
290      pseudo_bit_t	c[0x00001];            /* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */
291      pseudo_bit_t	ip[0x00001];           /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
292      pseudo_bit_t	tcp_udp[0x00001];      /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
293      pseudo_bit_t	reserved0[0x00001];
294      pseudo_bit_t	so[0x00001];           /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
295      pseudo_bit_t	reserved1[0x00018];
296  /* -------------- */
297      pseudo_bit_t	immediate[0x00020];    /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
298  /* -------------- */
299  };
300  
301  /* Send wqe segment next */
302  
303  struct arbelprm_wqe_segment_next_st {	/* Little Endian */
304      pseudo_bit_t	nopcode[0x00005];      /* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP:
305                                                   ?00000? - NOP. WQE with this opcode creates a completion, but does nothing else
306                                                   ?01000? - RDMA-write
307                                                   ?01001? - RDMA-Write with Immediate
308                                                   ?10000? - RDMA-read
309                                                   ?10001? - Atomic Compare & swap
310                                                   ?10010? - Atomic Fetch & Add
311                                                   ?11000? - Bind memory window
312  
313                                                   The encoding for the following operations depends on the QP type:
314                                                   For RC, UC and RD QP:
315                                                   ?01010? - SEND
316                                                   ?01011? - SEND with Immediate
317  
318                                                   For UD QP:
319                                                   the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of
320                                                   both  the current WQE and the next WQE, as follows:
321  
322                                                   If  the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set :
323                                                   ?01000? - SEND
324                                                   ?01001? - SEND with Immediate
325  
326                                                   otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set):
327                                                   ?01010? - SEND
328                                                   ?01011? - SEND with Immediate
329  
330                                                   All other opcode values are RESERVED, and will result in invalid operation execution. */
331      pseudo_bit_t	reserved0[0x00001];
332      pseudo_bit_t	nda_31_6[0x0001a];     /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
333  /* -------------- */
334      pseudo_bit_t	nds[0x00006];          /* Next WQE size in OctoWords (16 bytes).
335                                                   Zero value in NDS field signals end of WQEs? chain.
336                                                    */
337      pseudo_bit_t	f[0x00001];            /* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */
338      pseudo_bit_t	always1[0x00001];
339      pseudo_bit_t	reserved1[0x00018];
340  /* -------------- */
341  };
342  
343  /* Address Path */
344  
345  struct arbelprm_address_path_st {	/* Little Endian */
346      pseudo_bit_t	pkey_index[0x00007];   /* PKey table index */
347      pseudo_bit_t	reserved0[0x00011];
348      pseudo_bit_t	port_number[0x00002];  /* Specific port associated with this QP/EE.
349                                                   1 - Port 1
350                                                   2 - Port 2
351                                                   other - reserved */
352      pseudo_bit_t	reserved1[0x00006];
353  /* -------------- */
354      pseudo_bit_t	rlid[0x00010];         /* Remote (Destination) LID */
355      pseudo_bit_t	my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
356      pseudo_bit_t	g[0x00001];            /* Global address enable - if set, GRH will be formed for packet header */
357      pseudo_bit_t	reserved2[0x00005];
358      pseudo_bit_t	rnr_retry[0x00003];    /* RNR retry count (see C9-132 in IB spec Vol 1)
359                                                   0-6 - number of retries
360                                                   7    - infinite */
361  /* -------------- */
362      pseudo_bit_t	hop_limit[0x00008];    /* IPv6 hop limit */
363      pseudo_bit_t	max_stat_rate[0x00003];/* Maximum static rate control.
364                                                   0 - 100% injection rate
365                                                   1 - 25% injection rate
366                                                   2 - 12.5% injection rate
367                                                   3 - 50% injection rate
368                                                   other - reserved */
369      pseudo_bit_t	reserved3[0x00005];
370      pseudo_bit_t	mgid_index[0x00006];   /* Index to port GID table */
371      pseudo_bit_t	reserved4[0x00005];
372      pseudo_bit_t	ack_timeout[0x00005];  /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
373                                                   The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
374  /* -------------- */
375      pseudo_bit_t	flow_label[0x00014];   /* IPv6 flow label */
376      pseudo_bit_t	tclass[0x00008];       /* IPv6 TClass */
377      pseudo_bit_t	sl[0x00004];           /* InfiniBand Service Level (SL) */
378  /* -------------- */
379      pseudo_bit_t	rgid_127_96[0x00020];  /* Remote GID[127:96] */
380  /* -------------- */
381      pseudo_bit_t	rgid_95_64[0x00020];   /* Remote GID[95:64] */
382  /* -------------- */
383      pseudo_bit_t	rgid_63_32[0x00020];   /* Remote GID[63:32] */
384  /* -------------- */
385      pseudo_bit_t	rgid_31_0[0x00020];    /* Remote GID[31:0] */
386  /* -------------- */
387  };
388  
389  /* HCA Command Register (HCR) */
390  
391  struct arbelprm_hca_command_register_st {	/* Little Endian */
392      pseudo_bit_t	in_param_h[0x00020];   /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */
393  /* -------------- */
394      pseudo_bit_t	in_param_l[0x00020];   /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */
395  /* -------------- */
396      pseudo_bit_t	input_modifier[0x00020];/* Input Parameter Modifier */
397  /* -------------- */
398      pseudo_bit_t	out_param_h[0x00020];  /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
399  /* -------------- */
400      pseudo_bit_t	out_param_l[0x00020];  /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
401  /* -------------- */
402      pseudo_bit_t	reserved0[0x00010];
403      pseudo_bit_t	token[0x00010];        /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
404  /* -------------- */
405      pseudo_bit_t	opcode[0x0000c];       /* Command opcode */
406      pseudo_bit_t	opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
407      pseudo_bit_t	reserved1[0x00006];
408      pseudo_bit_t	e[0x00001];            /* Event Request
409                                                   0 - Don't report event (software will poll the GO bit)
410                                                   1 - Report event to EQ when the command completes */
411      pseudo_bit_t	go[0x00001];           /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
412                                                   Software can write to the HCR only if Go bit is cleared.
413                                                   Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
414      pseudo_bit_t	status[0x00008];       /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
415                                                   0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
416  /* -------------- */
417  };
418  
419  /* CQ Doorbell */
420  
421  struct arbelprm_cq_cmd_doorbell_st {	/* Little Endian */
422      pseudo_bit_t	cqn[0x00018];          /* CQ number accessed */
423      pseudo_bit_t	cmd[0x00003];          /* Command to be executed on CQ
424                                                   0x0 - Reserved
425                                                   0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter.
426                                                   0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter.
427                                                   0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated
428                                                   Other - Reserved */
429      pseudo_bit_t	reserved0[0x00001];
430      pseudo_bit_t	cmd_sn[0x00002];       /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ.
431                                                   This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited
432                                                   completion or Request notification for multiple completions doorbells after receiving completion notification.
433                                                   This field is initialized to Zero */
434      pseudo_bit_t	reserved1[0x00002];
435  /* -------------- */
436      pseudo_bit_t	cq_param[0x00020];     /* parameter to be used by CQ command */
437  /* -------------- */
438  };
439  
440  /* RD-send doorbell */
441  
442  struct arbelprm_rd_send_doorbell_st {	/* Little Endian */
443      pseudo_bit_t	reserved0[0x00008];
444      pseudo_bit_t	een[0x00018];          /* End-to-end context number (reliable datagram)
445                                                   Must be zero for Nop and Bind operations */
446  /* -------------- */
447      pseudo_bit_t	reserved1[0x00008];
448      pseudo_bit_t	qpn[0x00018];          /* QP number this doorbell is rung on */
449  /* -------------- */
450      struct arbelprm_send_doorbell_st	send_doorbell;/* Send Parameters */
451  /* -------------- */
452  };
453  
454  /* Multicast Group Member QP */
455  
456  struct arbelprm_mgmqp_st {	/* Little Endian */
457      pseudo_bit_t	qpn_i[0x00018];        /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
458      pseudo_bit_t	reserved0[0x00007];
459      pseudo_bit_t	qi[0x00001];           /* Qi: QPN_i is valid */
460  /* -------------- */
461  };
462  
463  /* vsd */
464  
465  struct arbelprm_vsd_st {	/* Little Endian */
466      pseudo_bit_t	vsd_dw0[0x00020];
467  /* -------------- */
468      pseudo_bit_t	vsd_dw1[0x00020];
469  /* -------------- */
470      pseudo_bit_t	vsd_dw2[0x00020];
471  /* -------------- */
472      pseudo_bit_t	vsd_dw3[0x00020];
473  /* -------------- */
474      pseudo_bit_t	vsd_dw4[0x00020];
475  /* -------------- */
476      pseudo_bit_t	vsd_dw5[0x00020];
477  /* -------------- */
478      pseudo_bit_t	vsd_dw6[0x00020];
479  /* -------------- */
480      pseudo_bit_t	vsd_dw7[0x00020];
481  /* -------------- */
482      pseudo_bit_t	vsd_dw8[0x00020];
483  /* -------------- */
484      pseudo_bit_t	vsd_dw9[0x00020];
485  /* -------------- */
486      pseudo_bit_t	vsd_dw10[0x00020];
487  /* -------------- */
488      pseudo_bit_t	vsd_dw11[0x00020];
489  /* -------------- */
490      pseudo_bit_t	vsd_dw12[0x00020];
491  /* -------------- */
492      pseudo_bit_t	vsd_dw13[0x00020];
493  /* -------------- */
494      pseudo_bit_t	vsd_dw14[0x00020];
495  /* -------------- */
496      pseudo_bit_t	vsd_dw15[0x00020];
497  /* -------------- */
498      pseudo_bit_t	vsd_dw16[0x00020];
499  /* -------------- */
500      pseudo_bit_t	vsd_dw17[0x00020];
501  /* -------------- */
502      pseudo_bit_t	vsd_dw18[0x00020];
503  /* -------------- */
504      pseudo_bit_t	vsd_dw19[0x00020];
505  /* -------------- */
506      pseudo_bit_t	vsd_dw20[0x00020];
507  /* -------------- */
508      pseudo_bit_t	vsd_dw21[0x00020];
509  /* -------------- */
510      pseudo_bit_t	vsd_dw22[0x00020];
511  /* -------------- */
512      pseudo_bit_t	vsd_dw23[0x00020];
513  /* -------------- */
514      pseudo_bit_t	vsd_dw24[0x00020];
515  /* -------------- */
516      pseudo_bit_t	vsd_dw25[0x00020];
517  /* -------------- */
518      pseudo_bit_t	vsd_dw26[0x00020];
519  /* -------------- */
520      pseudo_bit_t	vsd_dw27[0x00020];
521  /* -------------- */
522      pseudo_bit_t	vsd_dw28[0x00020];
523  /* -------------- */
524      pseudo_bit_t	vsd_dw29[0x00020];
525  /* -------------- */
526      pseudo_bit_t	vsd_dw30[0x00020];
527  /* -------------- */
528      pseudo_bit_t	vsd_dw31[0x00020];
529  /* -------------- */
530      pseudo_bit_t	vsd_dw32[0x00020];
531  /* -------------- */
532      pseudo_bit_t	vsd_dw33[0x00020];
533  /* -------------- */
534      pseudo_bit_t	vsd_dw34[0x00020];
535  /* -------------- */
536      pseudo_bit_t	vsd_dw35[0x00020];
537  /* -------------- */
538      pseudo_bit_t	vsd_dw36[0x00020];
539  /* -------------- */
540      pseudo_bit_t	vsd_dw37[0x00020];
541  /* -------------- */
542      pseudo_bit_t	vsd_dw38[0x00020];
543  /* -------------- */
544      pseudo_bit_t	vsd_dw39[0x00020];
545  /* -------------- */
546      pseudo_bit_t	vsd_dw40[0x00020];
547  /* -------------- */
548      pseudo_bit_t	vsd_dw41[0x00020];
549  /* -------------- */
550      pseudo_bit_t	vsd_dw42[0x00020];
551  /* -------------- */
552      pseudo_bit_t	vsd_dw43[0x00020];
553  /* -------------- */
554      pseudo_bit_t	vsd_dw44[0x00020];
555  /* -------------- */
556      pseudo_bit_t	vsd_dw45[0x00020];
557  /* -------------- */
558      pseudo_bit_t	vsd_dw46[0x00020];
559  /* -------------- */
560      pseudo_bit_t	vsd_dw47[0x00020];
561  /* -------------- */
562      pseudo_bit_t	vsd_dw48[0x00020];
563  /* -------------- */
564      pseudo_bit_t	vsd_dw49[0x00020];
565  /* -------------- */
566      pseudo_bit_t	vsd_dw50[0x00020];
567  /* -------------- */
568      pseudo_bit_t	vsd_dw51[0x00020];
569  /* -------------- */
570      pseudo_bit_t	vsd_dw52[0x00020];
571  /* -------------- */
572      pseudo_bit_t	vsd_dw53[0x00020];
573  /* -------------- */
574      pseudo_bit_t	vsd_dw54[0x00020];
575  /* -------------- */
576      pseudo_bit_t	vsd_dw55[0x00020];
577  /* -------------- */
578  };
579  
580  /* ACCESS_LAM_inject_errors */
581  
582  struct arbelprm_access_lam_inject_errors_st {	/* Little Endian */
583      struct arbelprm_access_lam_inject_errors_input_parameter_st	access_lam_inject_errors_input_parameter;
584  /* -------------- */
585      struct arbelprm_access_lam_inject_errors_input_modifier_st	access_lam_inject_errors_input_modifier;
586  /* -------------- */
587      pseudo_bit_t	reserved0[0x00020];
588  /* -------------- */
589  };
590  
591  /* Logical DIMM Information */
592  
593  struct arbelprm_dimminfo_st {	/* Little Endian */
594      pseudo_bit_t	dimmsize[0x00010];     /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */
595      pseudo_bit_t	reserved0[0x00008];
596      pseudo_bit_t	dimmstatus[0x00001];   /* DIMM Status
597                                                   0 - Enabled
598                                                   1 - Disabled
599                                                    */
600      pseudo_bit_t	dh[0x00001];           /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */
601      pseudo_bit_t	wo[0x00001];           /* When set, the DIMM is write only.
602                                                   If data integrity is configured (other than none), the DIMM must be
603                                                   only targeted by write transactions where the address and size are multiples of 16 bytes. */
604      pseudo_bit_t	reserved1[0x00005];
605  /* -------------- */
606      pseudo_bit_t	spd[0x00001];          /* 0 - DIMM SPD was read from DIMM
607                                                   1 - DIMM SPD was read from InfiniHost-III-EX NVMEM */
608      pseudo_bit_t	sladr[0x00003];        /* SPD Slave Address 3 LSBits.
609                                                   Valid only if spd bit is 0. */
610      pseudo_bit_t	sock_num[0x00002];     /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */
611      pseudo_bit_t	syn[0x00004];          /* Error syndrome (valid regardless of status value)
612                                                   0 - DIMM has no error
613                                                   1 - SPD error (e.g. checksum error, no response, error while reading)
614                                                   2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)
615                                                   3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)
616                                                   5 - DIMM size trimmed due to configuration (size exceeds)
617                                                   other - Error, reserved
618                                                    */
619      pseudo_bit_t	reserved2[0x00016];
620  /* -------------- */
621      pseudo_bit_t	reserved3[0x00040];
622  /* -------------- */
623      pseudo_bit_t	dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */
624  /* -------------- */
625      pseudo_bit_t	dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */
626  /* -------------- */
627      pseudo_bit_t	reserved4[0x00040];
628  /* -------------- */
629  };
630  
631  /* UAR Parameters */
632  
633  struct arbelprm_uar_params_st {	/* Little Endian */
634      pseudo_bit_t	uar_base_addr_h[0x00020];/* UAR Base (pyhsical) Address [63:32] (QUERY_HCA only) */
635  /* -------------- */
636      pseudo_bit_t	reserved0[0x00014];
637      pseudo_bit_t	uar_base_addr_l[0x0000c];/* UAR Base (pyhsical) Address [31:20] (QUERY_HCA only) */
638  /* -------------- */
639      pseudo_bit_t	uar_page_sz[0x00008];  /* This field defines the size of each UAR page.
640                                                   Size of UAR Page is 4KB*2^UAR_Page_Size */
641      pseudo_bit_t	log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */
642      pseudo_bit_t	reserved1[0x00004];
643      pseudo_bit_t	log_uar_entry_sz[0x00006];/* Size of UAR Context entry is 2^log_uar_sz in 4KByte pages */
644      pseudo_bit_t	reserved2[0x0000a];
645  /* -------------- */
646      pseudo_bit_t	reserved3[0x00020];
647  /* -------------- */
648      pseudo_bit_t	uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32].
649                                                   Number of entries in table is 2^log_max_uars.
650                                                   Table must be aligned to its size */
651  /* -------------- */
652      pseudo_bit_t	uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0].
653                                                   Number of entries in table is 2^log_max_uars.
654                                                   Table must be aligned to its size. */
655  /* -------------- */
656      pseudo_bit_t	uar_context_base_addr_h[0x00020];/* Base address of UAR Context [63:32].
657                                                   Number of entries in table is 2^log_max_uars.
658                                                   Table must be aligned to its size. */
659  /* -------------- */
660      pseudo_bit_t	uar_context_base_addr_l[0x00020];/* Base address of UAR Context [31:0].
661                                                   Number of entries in table is 2^log_max_uars.
662                                                   Table must be aligned to its size. */
663  /* -------------- */
664  };
665  
666  /* Translation and Protection Tables Parameters */
667  
668  struct arbelprm_tptparams_st {	/* Little Endian */
669      pseudo_bit_t	mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32].
670                                                   Entry size is 64 bytes.
671                                                   Table must be aligned to its size.
672                                                   Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
673  /* -------------- */
674      pseudo_bit_t	mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0].
675                                                   Entry size is 64 bytes.
676                                                   Table must be aligned to its size.
677                                                   Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
678  /* -------------- */
679      pseudo_bit_t	log_mpt_sz[0x00006];   /* Log (base 2) of the number of region/windows entries in the MPT table. */
680      pseudo_bit_t	reserved0[0x00002];
681      pseudo_bit_t	pfto[0x00005];         /* Page Fault RNR Timeout -
682                                                   The field returned in RNR Naks generated when a page fault is detected.
683                                                   It has no effect when on-demand-paging is not used. */
684      pseudo_bit_t	reserved1[0x00013];
685  /* -------------- */
686      pseudo_bit_t	reserved2[0x00020];
687  /* -------------- */
688      pseudo_bit_t	mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].
689                                                   Table must be aligned to its size.
690                                                   Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
691  /* -------------- */
692      pseudo_bit_t	mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].
693                                                   Table must be aligned to its size.
694                                                   Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
695  /* -------------- */
696      pseudo_bit_t	reserved3[0x00040];
697  /* -------------- */
698  };
699  
700  /* Multicast Support Parameters */
701  
702  struct arbelprm_multicastparam_st {	/* Little Endian */
703      pseudo_bit_t	mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].
704                                                   The base address must be aligned to the entry size.
705                                                   Address may be set to 0xFFFFFFFF if multicast is not supported. */
706  /* -------------- */
707      pseudo_bit_t	mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0].
708                                                   The base address must be aligned to the entry size.
709                                                   Address may be set to 0xFFFFFFFF if multicast is not supported. */
710  /* -------------- */
711      pseudo_bit_t	reserved0[0x00040];
712  /* -------------- */
713      pseudo_bit_t	log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry.
714                                                   Must be greater than 5 (to allow CTRL and GID sections).
715                                                   That implies the number of QPs per MC table entry. */
716      pseudo_bit_t	reserved1[0x00010];
717  /* -------------- */
718      pseudo_bit_t	mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2)
719                                                   INIT_HCA - the required number of entries
720                                                   QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */
721      pseudo_bit_t	reserved2[0x0000f];
722  /* -------------- */
723      pseudo_bit_t	log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
724      pseudo_bit_t	reserved3[0x00013];
725      pseudo_bit_t	mc_hash_fn[0x00003];   /* Multicast hash function
726                                                   0 - Default hash function
727                                                   other - reserved */
728      pseudo_bit_t	reserved4[0x00005];
729  /* -------------- */
730      pseudo_bit_t	reserved5[0x00020];
731  /* -------------- */
732  };
733  
734  /* QPC/EEC/CQC/EQC/RDB Parameters */
735  
736  struct arbelprm_qpcbaseaddr_st {	/* Little Endian */
737      pseudo_bit_t	reserved0[0x00080];
738  /* -------------- */
739      pseudo_bit_t	qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
740                                                   Table must be aligned on its size */
741  /* -------------- */
742      pseudo_bit_t	log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
743      pseudo_bit_t	reserved1[0x00002];
744      pseudo_bit_t	qpc_base_addr_l[0x00019];/* QPC Base Address [31:7]
745                                                   Table must be aligned on its size */
746  /* -------------- */
747      pseudo_bit_t	reserved2[0x00040];
748  /* -------------- */
749      pseudo_bit_t	eec_base_addr_h[0x00020];/* EEC Base Address [63:32]
750                                                   Table must be aligned on its size.
751                                                   Address may be set to 0xFFFFFFFF if RD is not supported. */
752  /* -------------- */
753      pseudo_bit_t	log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */
754      pseudo_bit_t	reserved3[0x00002];
755      pseudo_bit_t	eec_base_addr_l[0x00019];/* EEC Base Address [31:7]
756                                                   Table must be aligned on its size
757                                                   Address may be set to 0xFFFFFFFF if RD is not supported. */
758  /* -------------- */
759      pseudo_bit_t	srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
760                                                   Table must be aligned on its size
761                                                   Address may be set to 0xFFFFFFFF if SRQ is not supported. */
762  /* -------------- */
763      pseudo_bit_t	log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
764      pseudo_bit_t	srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
765                                                   Table must be aligned on its size
766                                                   Address may be set to 0xFFFFFFFF if SRQ is not supported. */
767  /* -------------- */
768      pseudo_bit_t	cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
769                                                   Table must be aligned on its size */
770  /* -------------- */
771      pseudo_bit_t	log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
772      pseudo_bit_t	reserved4[0x00001];
773      pseudo_bit_t	cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6]
774                                                   Table must be aligned on its size */
775  /* -------------- */
776      pseudo_bit_t	reserved5[0x00040];
777  /* -------------- */
778      pseudo_bit_t	eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32]
779                                                   Table has same number of entries as QPC table.
780                                                   Table must be aligned to entry size. */
781  /* -------------- */
782      pseudo_bit_t	eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0]
783                                                   Table has same number of entries as QPC table.
784                                                   Table must be aligned to entry size. */
785  /* -------------- */
786      pseudo_bit_t	reserved6[0x00040];
787  /* -------------- */
788      pseudo_bit_t	eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32]
789                                                   Table has same number of entries as EEC table.
790                                                   Table must be aligned to entry size.
791                                                   Address may be set to 0xFFFFFFFF if RD is not supported. */
792  /* -------------- */
793      pseudo_bit_t	eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0]
794                                                   Table has same number of entries as EEC table.
795                                                   Table must be aligned to entry size.
796                                                   Address may be set to 0xFFFFFFFF if RD is not supported. */
797  /* -------------- */
798      pseudo_bit_t	reserved7[0x00040];
799  /* -------------- */
800      pseudo_bit_t	eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
801                                                   Address may be set to 0xFFFFFFFF if EQs are not supported.
802                                                   Table must be aligned to entry size. */
803  /* -------------- */
804      pseudo_bit_t	log_num_eq[0x00004];   /* Log base 2 of number of supported EQs.
805                                                   Must be 6 or less in InfiniHost-III-EX. */
806      pseudo_bit_t	reserved8[0x00002];
807      pseudo_bit_t	eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6]
808                                                   Address may be set to 0xFFFFFFFF if EQs are not supported.
809                                                   Table must be aligned to entry size. */
810  /* -------------- */
811      pseudo_bit_t	reserved9[0x00040];
812  /* -------------- */
813      pseudo_bit_t	rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32].
814                                                   Address may be set to 0xFFFFFFFF if remote RDMA reads are not supported.
815                                                   Please refer to QP and EE chapter for further explanation on RDB allocation. */
816  /* -------------- */
817      pseudo_bit_t	rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0].
818                                                   Table must be aligned to RDB entry size (32 bytes).
819                                                   Address may be set to zero if remote RDMA reads are not supported.
820                                                   Please refer to QP and EE chapter for further explanation on RDB allocation. */
821  /* -------------- */
822      pseudo_bit_t	reserved10[0x00040];
823  /* -------------- */
824  };
825  
826  /* Header_Log_Register */
827  
828  struct arbelprm_header_log_register_st {	/* Little Endian */
829      pseudo_bit_t	place_holder[0x00020];
830  /* -------------- */
831      pseudo_bit_t	reserved0[0x00060];
832  /* -------------- */
833  };
834  
835  /* Performance Monitors */
836  
837  struct arbelprm_performance_monitors_st {	/* Little Endian */
838      pseudo_bit_t	e0[0x00001];           /* Enables counting of respective performance counter */
839      pseudo_bit_t	e1[0x00001];           /* Enables counting of respective performance counter */
840      pseudo_bit_t	e2[0x00001];           /* Enables counting of respective performance counter */
841      pseudo_bit_t	reserved0[0x00001];
842      pseudo_bit_t	r0[0x00001];           /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
843      pseudo_bit_t	r1[0x00001];           /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
844      pseudo_bit_t	r2[0x00001];           /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
845      pseudo_bit_t	reserved1[0x00001];
846      pseudo_bit_t	i0[0x00001];           /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
847      pseudo_bit_t	i1[0x00001];           /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
848      pseudo_bit_t	i2[0x00001];           /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
849      pseudo_bit_t	reserved2[0x00001];
850      pseudo_bit_t	f0[0x00001];           /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
851      pseudo_bit_t	f1[0x00001];           /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
852      pseudo_bit_t	f2[0x00001];           /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
853      pseudo_bit_t	reserved3[0x00001];
854      pseudo_bit_t	ev_cnt1[0x00005];      /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
855      pseudo_bit_t	reserved4[0x00003];
856      pseudo_bit_t	ev_cnt2[0x00005];      /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
857      pseudo_bit_t	reserved5[0x00003];
858  /* -------------- */
859      pseudo_bit_t	clock_counter[0x00020];
860  /* -------------- */
861      pseudo_bit_t	event_counter1[0x00020];
862  /* -------------- */
863      pseudo_bit_t	event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
864  /* -------------- */
865  };
866  
867  /* Receive segment format */
868  
869  struct arbelprm_wqe_segment_ctrl_recv_st {	/* Little Endian */
870      struct arbelprm_recv_wqe_segment_next_st	wqe_segment_next;
871  /* -------------- */
872      pseudo_bit_t	reserved0[0x00002];
873      pseudo_bit_t	reserved1[0x00001];
874      pseudo_bit_t	reserved2[0x00001];
875      pseudo_bit_t	reserved3[0x0001c];
876  /* -------------- */
877      pseudo_bit_t	reserved4[0x00020];
878  /* -------------- */
879  };
880  
881  /* MLX WQE segment format */
882  
883  struct arbelprm_wqe_segment_ctrl_mlx_st {	/* Little Endian */
884      pseudo_bit_t	reserved0[0x00002];
885      pseudo_bit_t	e[0x00001];            /* WQE event */
886      pseudo_bit_t	c[0x00001];            /* Create CQE (for "requested signalling" QP) */
887      pseudo_bit_t	icrc[0x00002];         /* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved.  3 - Leave last dword as is. Last dword must not be 0x0. */
888      pseudo_bit_t	reserved1[0x00002];
889      pseudo_bit_t	sl[0x00004];
890      pseudo_bit_t	max_statrate[0x00004];
891      pseudo_bit_t	slr[0x00001];          /* 0= take slid from port. 1= take slid from given headers */
892      pseudo_bit_t	v15[0x00001];          /* Send packet over VL15 */
893      pseudo_bit_t	reserved2[0x0000e];
894  /* -------------- */
895      pseudo_bit_t	vcrc[0x00010];         /* Packet's VCRC (if not 0 - otherwise computed by HW) */
896      pseudo_bit_t	rlid[0x00010];         /* Destination LID (must match given headers) */
897  /* -------------- */
898      pseudo_bit_t	reserved3[0x00040];
899  /* -------------- */
900  };
901  
902  /* Send WQE segment format */
903  
904  struct arbelprm_send_wqe_segment_st {	/* Little Endian */
905      struct arbelprm_wqe_segment_next_st	wqe_segment_next;/* Send wqe segment next */
906  /* -------------- */
907      struct arbelprm_wqe_segment_ctrl_send_st	wqe_segment_ctrl_send;/* Send wqe segment ctrl */
908  /* -------------- */
909      struct arbelprm_wqe_segment_rd_st	wqe_segment_rd;/* Send wqe segment rd */
910  /* -------------- */
911      struct arbelprm_wqe_segment_ud_st	wqe_segment_ud;/* Send wqe segment ud */
912  /* -------------- */
913      struct arbelprm_wqe_segment_bind_st	wqe_segment_bind;/* Send wqe segment bind */
914  /* -------------- */
915      pseudo_bit_t	reserved0[0x00180];
916  /* -------------- */
917      struct arbelprm_wqe_segment_remote_address_st	wqe_segment_remote_address;/* Send wqe segment remote address */
918  /* -------------- */
919      struct arbelprm_wqe_segment_atomic_st	wqe_segment_atomic;/* Send wqe segment atomic */
920  /* -------------- */
921      struct arbelprm_fast_registration_segment_st	fast_registration_segment;/* Fast Registration Segment */
922  /* -------------- */
923      struct arbelprm_local_invalidate_segment_st	local_invalidate_segment;/* local invalidate segment */
924  /* -------------- */
925      struct arbelprm_wqe_segment_data_ptr_st	wqe_segment_data_ptr;/* Send wqe segment data ptr */
926  /* -------------- */
927      struct arbelprm_wqe_segment_data_inline_st	wqe_segment_data_inline;/* Send wqe segment data inline */
928  /* -------------- */
929      pseudo_bit_t	reserved1[0x00200];
930  /* -------------- */
931  };
932  
933  /* QP and EE Context Entry */
934  
935  struct arbelprm_queue_pair_ee_context_entry_st {	/* Little Endian */
936      pseudo_bit_t	reserved0[0x00008];
937      pseudo_bit_t	de[0x00001];           /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */
938      pseudo_bit_t	reserved1[0x00002];
939      pseudo_bit_t	pm_state[0x00002];     /* Path migration state (Migrated, Armed or Rearm)
940                                                   11-Migrated
941                                                   00-Armed
942                                                   01-Rearm
943                                                   10-Reserved
944                                                   Should be set to 11 for UD QPs and for QPs which do not support APM */
945      pseudo_bit_t	reserved2[0x00003];
946      pseudo_bit_t	st[0x00003];           /* Service type (invalid in EE context):
947                                                   000-Reliable Connection
948                                                   001-Unreliable Connection
949                                                   010-Reliable Datagram
950                                                   011-Unreliable Datagram
951                                                   111-MLX transport (raw bits injection). Used for management QPs and RAW */
952      pseudo_bit_t	reserved3[0x00009];
953      pseudo_bit_t	state[0x00004];        /* QP/EE state:
954                                                   0 - RST
955                                                   1 - INIT
956                                                   2 - RTR
957                                                   3 - RTS
958                                                   4 - SQEr
959                                                   5 - SQD (Send Queue Drained)
960                                                   6 - ERR
961                                                   7 - Send Queue Draining
962                                                   8 - Reserved
963                                                   9 - Suspended
964                                                   A- F - Reserved
965                                                   (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
966  /* -------------- */
967      pseudo_bit_t	reserved4[0x00020];
968  /* -------------- */
969      pseudo_bit_t	sched_queue[0x00004];  /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */
970      pseudo_bit_t	rlky[0x00001];         /* When set this QP can use the Reserved L_Key */
971      pseudo_bit_t	reserved5[0x00003];
972      pseudo_bit_t	log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes.
973                                                   Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
974      pseudo_bit_t	log_sq_size[0x00004];  /* Log2 of the Number of WQEs in the Send Queue. */
975      pseudo_bit_t	reserved6[0x00001];
976      pseudo_bit_t	log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes.
977                                                   Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
978      pseudo_bit_t	log_rq_size[0x00004];  /* Log2 of the Number of WQEs in the Receive Queue. */
979      pseudo_bit_t	reserved7[0x00001];
980      pseudo_bit_t	msg_max[0x00005];      /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
981                                                   Must be equal to MTU for UD and MLX QPs. */
982      pseudo_bit_t	mtu[0x00003];          /* MTU of the QP (Must be the same for both paths: primary and alternative):
983                                                   0x1 - 256 bytes
984                                                   0x2 - 512
985                                                   0x3 - 1024
986                                                   0x4 - 2048
987                                                   other - reserved
988  
989                                                   Should be configured to 0x4 for UD and MLX QPs. */
990  /* -------------- */
991      pseudo_bit_t	usr_page[0x00018];     /* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
992      pseudo_bit_t	reserved8[0x00008];
993  /* -------------- */
994      pseudo_bit_t	local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
995                                                   This field is valid for QUERY and ERR2RST commands only. */
996      pseudo_bit_t	reserved9[0x00008];
997  /* -------------- */
998      pseudo_bit_t	remote_qpn_een[0x00018];/* Remote QP/EE number */
999      pseudo_bit_t	reserved10[0x00008];
1000  /* -------------- */
1001      pseudo_bit_t	reserved11[0x00040];
1002  /* -------------- */
1003      struct arbelprm_address_path_st	primary_address_path;/* Primary address path for the QP/EE */
1004  /* -------------- */
1005      struct arbelprm_address_path_st	alternative_address_path;/* Alternate address path for the QP/EE */
1006  /* -------------- */
1007      pseudo_bit_t	rdd[0x00018];          /* Reliable Datagram Domain */
1008      pseudo_bit_t	reserved12[0x00008];
1009  /* -------------- */
1010      pseudo_bit_t	pd[0x00018];           /* QP protection domain. Not valid (reserved) in EE context. */
1011      pseudo_bit_t	reserved13[0x00008];
1012  /* -------------- */
1013      pseudo_bit_t	wqe_base_adr_h[0x00020];/* Bits 63:32 of WQE address for both SQ and RQ.
1014                                                   Reserved for EE context. */
1015  /* -------------- */
1016      pseudo_bit_t	wqe_lkey[0x00020];     /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */
1017  /* -------------- */
1018      pseudo_bit_t	reserved14[0x00003];
1019      pseudo_bit_t	ssc[0x00001];          /* Send Signaled Completion
1020                                                   1 - all send WQEs generate CQEs.
1021                                                   0 - only send WQEs with C bit set generate completion.
1022                                                   Not valid (reserved) in EE context. */
1023      pseudo_bit_t	sic[0x00001];          /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */
1024      pseudo_bit_t	cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
1025                                                   The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
1026      pseudo_bit_t	cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
1027                                                   The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
1028      pseudo_bit_t	fre[0x00001];          /* Fast Registration Work Request Enabled. (Reserved for EE) */
1029      pseudo_bit_t	reserved15[0x00001];
1030      pseudo_bit_t	sae[0x00001];          /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */
1031      pseudo_bit_t	swe[0x00001];          /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */
1032      pseudo_bit_t	sre[0x00001];          /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */
1033      pseudo_bit_t	retry_count[0x00003];  /* Transport timeout Retry count */
1034      pseudo_bit_t	reserved16[0x00002];
1035      pseudo_bit_t	sra_max[0x00003];      /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
1036      pseudo_bit_t	flight_lim[0x00004];   /* Number of outstanding (in-flight) messages on the wire allowed for this send queue.
1037                                                   Number of outstanding messages is 2^Flight_Lim.
1038                                                   Use 0xF for unlimited number of outstanding messages. */
1039      pseudo_bit_t	ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
1040  /* -------------- */
1041      pseudo_bit_t	reserved17[0x00020];
1042  /* -------------- */
1043      pseudo_bit_t	next_send_psn[0x00018];/* Next PSN to be sent */
1044      pseudo_bit_t	reserved18[0x00008];
1045  /* -------------- */
1046      pseudo_bit_t	cqn_snd[0x00018];      /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
1047      pseudo_bit_t	reserved19[0x00008];
1048  /* -------------- */
1049      pseudo_bit_t	reserved20[0x00006];
1050      pseudo_bit_t	snd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
1051  /* -------------- */
1052      pseudo_bit_t	snd_db_record_index[0x00020];/* Index in the UAR Context Table Entry.
1053                                                   HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record.
1054                                                   The entry is obtained via the usr_page field.
1055                                                   Not valid for EE. */
1056  /* -------------- */
1057      pseudo_bit_t	last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
1058      pseudo_bit_t	reserved21[0x00008];
1059  /* -------------- */
1060      pseudo_bit_t	ssn[0x00018];          /* Requester Send Sequence Number (QUERY_QPEE only) */
1061      pseudo_bit_t	reserved22[0x00008];
1062  /* -------------- */
1063      pseudo_bit_t	reserved23[0x00003];
1064      pseudo_bit_t	rsc[0x00001];          /* 1 - all receive WQEs generate CQEs.
1065                                                   0 - only receive WQEs with C bit set generate completion.
1066                                                   Not valid (reserved) in EE context.
1067                                                    */
1068      pseudo_bit_t	ric[0x00001];          /* Invalid Credits.
1069                                                   1 - place "Invalid Credits" to ACKs sent from this queue.
1070                                                   0 - ACKs report the actual number of end to end credits on the connection.
1071                                                   Not valid (reserved) in EE context.
1072                                                   Must be set to 1 on QPs which are attached to SRQ. */
1073      pseudo_bit_t	reserved24[0x00008];
1074      pseudo_bit_t	rae[0x00001];          /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
1075      pseudo_bit_t	rwe[0x00001];          /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
1076      pseudo_bit_t	rre[0x00001];          /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
1077      pseudo_bit_t	reserved25[0x00005];
1078      pseudo_bit_t	rra_max[0x00003];      /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max.
1079                                                   Must be 0 for EE context. */
1080      pseudo_bit_t	reserved26[0x00008];
1081  /* -------------- */
1082      pseudo_bit_t	next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */
1083      pseudo_bit_t	min_rnr_nak[0x00005];  /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8).
1084                                                   Not valid (reserved) in EE context. */
1085      pseudo_bit_t	reserved27[0x00003];
1086  /* -------------- */
1087      pseudo_bit_t	reserved28[0x00005];
1088      pseudo_bit_t	ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer.
1089                                                   This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */
1090  /* -------------- */
1091      pseudo_bit_t	cqn_rcv[0x00018];      /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
1092      pseudo_bit_t	reserved29[0x00008];
1093  /* -------------- */
1094      pseudo_bit_t	reserved30[0x00006];
1095      pseudo_bit_t	rcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
1096  /* -------------- */
1097      pseudo_bit_t	rcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
1098                                                   HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record.
1099                                                   The entry is obtained via the usr_page field.
1100                                                   Not valid for EE. */
1101  /* -------------- */
1102      pseudo_bit_t	q_key[0x00020];        /* Q_Key to be validated against received datagrams.
1103                                                   On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
1104                                                   Not valid (reserved) in EE context. */
1105  /* -------------- */
1106      pseudo_bit_t	srqn[0x00018];         /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors.
1107                                                   SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
1108      pseudo_bit_t	srq[0x00001];          /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
1109      pseudo_bit_t	reserved31[0x00007];
1110  /* -------------- */
1111      pseudo_bit_t	rmsn[0x00018];         /* Responder current message sequence number (QUERY_QPEE only) */
1112      pseudo_bit_t	reserved32[0x00008];
1113  /* -------------- */
1114      pseudo_bit_t	sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
1115                                                   Must be 0x0 in SQ initialization.
1116                                                   (QUERY_QPEE only). */
1117      pseudo_bit_t	rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
1118                                                   Must be 0x0 in RQ initialization.
1119                                                   (QUERY_QPEE only). */
1120  /* -------------- */
1121      pseudo_bit_t	reserved33[0x00040];
1122  /* -------------- */
1123  };
1124  
1125  /* Clear Interrupt [63:0] */
1126  
1127  struct arbelprm_clr_int_st {	/* Little Endian */
1128      pseudo_bit_t	clr_int_h[0x00020];    /* Clear Interrupt [63:32]
1129                                                   Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1130                                                   This register is write-only. Reading from this register will cause undefined result
1131                                                    */
1132  /* -------------- */
1133      pseudo_bit_t	clr_int_l[0x00020];    /* Clear Interrupt [31:0]
1134                                                   Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1135                                                   This register is write-only. Reading from this register will cause undefined result */
1136  /* -------------- */
1137  };
1138  
1139  /* EQ_Arm_DB_Region */
1140  
1141  struct arbelprm_eq_arm_db_region_st {	/* Little Endian */
1142      pseudo_bit_t	eq_x_arm_h[0x00020];   /* EQ[63:32]  X state.
1143                                                   This register is used to Arm EQs when setting the appropriate bits. */
1144  /* -------------- */
1145      pseudo_bit_t	eq_x_arm_l[0x00020];   /* EQ[31:0]  X state.
1146                                                   This register is used to Arm EQs when setting the appropriate bits. */
1147  /* -------------- */
1148  };
1149  
1150  /* EQ Set CI DBs Table */
1151  
1152  struct arbelprm_eq_set_ci_table_st {	/* Little Endian */
1153      pseudo_bit_t	eq0_set_ci[0x00020];   /* EQ0_Set_CI */
1154  /* -------------- */
1155      pseudo_bit_t	reserved0[0x00020];
1156  /* -------------- */
1157      pseudo_bit_t	eq1_set_ci[0x00020];   /* EQ1_Set_CI */
1158  /* -------------- */
1159      pseudo_bit_t	reserved1[0x00020];
1160  /* -------------- */
1161      pseudo_bit_t	eq2_set_ci[0x00020];   /* EQ2_Set_CI */
1162  /* -------------- */
1163      pseudo_bit_t	reserved2[0x00020];
1164  /* -------------- */
1165      pseudo_bit_t	eq3_set_ci[0x00020];   /* EQ3_Set_CI */
1166  /* -------------- */
1167      pseudo_bit_t	reserved3[0x00020];
1168  /* -------------- */
1169      pseudo_bit_t	eq4_set_ci[0x00020];   /* EQ4_Set_CI */
1170  /* -------------- */
1171      pseudo_bit_t	reserved4[0x00020];
1172  /* -------------- */
1173      pseudo_bit_t	eq5_set_ci[0x00020];   /* EQ5_Set_CI */
1174  /* -------------- */
1175      pseudo_bit_t	reserved5[0x00020];
1176  /* -------------- */
1177      pseudo_bit_t	eq6_set_ci[0x00020];   /* EQ6_Set_CI */
1178  /* -------------- */
1179      pseudo_bit_t	reserved6[0x00020];
1180  /* -------------- */
1181      pseudo_bit_t	eq7_set_ci[0x00020];   /* EQ7_Set_CI */
1182  /* -------------- */
1183      pseudo_bit_t	reserved7[0x00020];
1184  /* -------------- */
1185      pseudo_bit_t	eq8_set_ci[0x00020];   /* EQ8_Set_CI */
1186  /* -------------- */
1187      pseudo_bit_t	reserved8[0x00020];
1188  /* -------------- */
1189      pseudo_bit_t	eq9_set_ci[0x00020];   /* EQ9_Set_CI */
1190  /* -------------- */
1191      pseudo_bit_t	reserved9[0x00020];
1192  /* -------------- */
1193      pseudo_bit_t	eq10_set_ci[0x00020];  /* EQ10_Set_CI */
1194  /* -------------- */
1195      pseudo_bit_t	reserved10[0x00020];
1196  /* -------------- */
1197      pseudo_bit_t	eq11_set_ci[0x00020];  /* EQ11_Set_CI */
1198  /* -------------- */
1199      pseudo_bit_t	reserved11[0x00020];
1200  /* -------------- */
1201      pseudo_bit_t	eq12_set_ci[0x00020];  /* EQ12_Set_CI */
1202  /* -------------- */
1203      pseudo_bit_t	reserved12[0x00020];
1204  /* -------------- */
1205      pseudo_bit_t	eq13_set_ci[0x00020];  /* EQ13_Set_CI */
1206  /* -------------- */
1207      pseudo_bit_t	reserved13[0x00020];
1208  /* -------------- */
1209      pseudo_bit_t	eq14_set_ci[0x00020];  /* EQ14_Set_CI */
1210  /* -------------- */
1211      pseudo_bit_t	reserved14[0x00020];
1212  /* -------------- */
1213      pseudo_bit_t	eq15_set_ci[0x00020];  /* EQ15_Set_CI */
1214  /* -------------- */
1215      pseudo_bit_t	reserved15[0x00020];
1216  /* -------------- */
1217      pseudo_bit_t	eq16_set_ci[0x00020];  /* EQ16_Set_CI */
1218  /* -------------- */
1219      pseudo_bit_t	reserved16[0x00020];
1220  /* -------------- */
1221      pseudo_bit_t	eq17_set_ci[0x00020];  /* EQ17_Set_CI */
1222  /* -------------- */
1223      pseudo_bit_t	reserved17[0x00020];
1224  /* -------------- */
1225      pseudo_bit_t	eq18_set_ci[0x00020];  /* EQ18_Set_CI */
1226  /* -------------- */
1227      pseudo_bit_t	reserved18[0x00020];
1228  /* -------------- */
1229      pseudo_bit_t	eq19_set_ci[0x00020];  /* EQ19_Set_CI */
1230  /* -------------- */
1231      pseudo_bit_t	reserved19[0x00020];
1232  /* -------------- */
1233      pseudo_bit_t	eq20_set_ci[0x00020];  /* EQ20_Set_CI */
1234  /* -------------- */
1235      pseudo_bit_t	reserved20[0x00020];
1236  /* -------------- */
1237      pseudo_bit_t	eq21_set_ci[0x00020];  /* EQ21_Set_CI */
1238  /* -------------- */
1239      pseudo_bit_t	reserved21[0x00020];
1240  /* -------------- */
1241      pseudo_bit_t	eq22_set_ci[0x00020];  /* EQ22_Set_CI */
1242  /* -------------- */
1243      pseudo_bit_t	reserved22[0x00020];
1244  /* -------------- */
1245      pseudo_bit_t	eq23_set_ci[0x00020];  /* EQ23_Set_CI */
1246  /* -------------- */
1247      pseudo_bit_t	reserved23[0x00020];
1248  /* -------------- */
1249      pseudo_bit_t	eq24_set_ci[0x00020];  /* EQ24_Set_CI */
1250  /* -------------- */
1251      pseudo_bit_t	reserved24[0x00020];
1252  /* -------------- */
1253      pseudo_bit_t	eq25_set_ci[0x00020];  /* EQ25_Set_CI */
1254  /* -------------- */
1255      pseudo_bit_t	reserved25[0x00020];
1256  /* -------------- */
1257      pseudo_bit_t	eq26_set_ci[0x00020];  /* EQ26_Set_CI */
1258  /* -------------- */
1259      pseudo_bit_t	reserved26[0x00020];
1260  /* -------------- */
1261      pseudo_bit_t	eq27_set_ci[0x00020];  /* EQ27_Set_CI */
1262  /* -------------- */
1263      pseudo_bit_t	reserved27[0x00020];
1264  /* -------------- */
1265      pseudo_bit_t	eq28_set_ci[0x00020];  /* EQ28_Set_CI */
1266  /* -------------- */
1267      pseudo_bit_t	reserved28[0x00020];
1268  /* -------------- */
1269      pseudo_bit_t	eq29_set_ci[0x00020];  /* EQ29_Set_CI */
1270  /* -------------- */
1271      pseudo_bit_t	reserved29[0x00020];
1272  /* -------------- */
1273      pseudo_bit_t	eq30_set_ci[0x00020];  /* EQ30_Set_CI */
1274  /* -------------- */
1275      pseudo_bit_t	reserved30[0x00020];
1276  /* -------------- */
1277      pseudo_bit_t	eq31_set_ci[0x00020];  /* EQ31_Set_CI */
1278  /* -------------- */
1279      pseudo_bit_t	reserved31[0x00020];
1280  /* -------------- */
1281      pseudo_bit_t	eq32_set_ci[0x00020];  /* EQ32_Set_CI */
1282  /* -------------- */
1283      pseudo_bit_t	reserved32[0x00020];
1284  /* -------------- */
1285      pseudo_bit_t	eq33_set_ci[0x00020];  /* EQ33_Set_CI */
1286  /* -------------- */
1287      pseudo_bit_t	reserved33[0x00020];
1288  /* -------------- */
1289      pseudo_bit_t	eq34_set_ci[0x00020];  /* EQ34_Set_CI */
1290  /* -------------- */
1291      pseudo_bit_t	reserved34[0x00020];
1292  /* -------------- */
1293      pseudo_bit_t	eq35_set_ci[0x00020];  /* EQ35_Set_CI */
1294  /* -------------- */
1295      pseudo_bit_t	reserved35[0x00020];
1296  /* -------------- */
1297      pseudo_bit_t	eq36_set_ci[0x00020];  /* EQ36_Set_CI */
1298  /* -------------- */
1299      pseudo_bit_t	reserved36[0x00020];
1300  /* -------------- */
1301      pseudo_bit_t	eq37_set_ci[0x00020];  /* EQ37_Set_CI */
1302  /* -------------- */
1303      pseudo_bit_t	reserved37[0x00020];
1304  /* -------------- */
1305      pseudo_bit_t	eq38_set_ci[0x00020];  /* EQ38_Set_CI */
1306  /* -------------- */
1307      pseudo_bit_t	reserved38[0x00020];
1308  /* -------------- */
1309      pseudo_bit_t	eq39_set_ci[0x00020];  /* EQ39_Set_CI */
1310  /* -------------- */
1311      pseudo_bit_t	reserved39[0x00020];
1312  /* -------------- */
1313      pseudo_bit_t	eq40_set_ci[0x00020];  /* EQ40_Set_CI */
1314  /* -------------- */
1315      pseudo_bit_t	reserved40[0x00020];
1316  /* -------------- */
1317      pseudo_bit_t	eq41_set_ci[0x00020];  /* EQ41_Set_CI */
1318  /* -------------- */
1319      pseudo_bit_t	reserved41[0x00020];
1320  /* -------------- */
1321      pseudo_bit_t	eq42_set_ci[0x00020];  /* EQ42_Set_CI */
1322  /* -------------- */
1323      pseudo_bit_t	reserved42[0x00020];
1324  /* -------------- */
1325      pseudo_bit_t	eq43_set_ci[0x00020];  /* EQ43_Set_CI */
1326  /* -------------- */
1327      pseudo_bit_t	reserved43[0x00020];
1328  /* -------------- */
1329      pseudo_bit_t	eq44_set_ci[0x00020];  /* EQ44_Set_CI */
1330  /* -------------- */
1331      pseudo_bit_t	reserved44[0x00020];
1332  /* -------------- */
1333      pseudo_bit_t	eq45_set_ci[0x00020];  /* EQ45_Set_CI */
1334  /* -------------- */
1335      pseudo_bit_t	reserved45[0x00020];
1336  /* -------------- */
1337      pseudo_bit_t	eq46_set_ci[0x00020];  /* EQ46_Set_CI */
1338  /* -------------- */
1339      pseudo_bit_t	reserved46[0x00020];
1340  /* -------------- */
1341      pseudo_bit_t	eq47_set_ci[0x00020];  /* EQ47_Set_CI */
1342  /* -------------- */
1343      pseudo_bit_t	reserved47[0x00020];
1344  /* -------------- */
1345      pseudo_bit_t	eq48_set_ci[0x00020];  /* EQ48_Set_CI */
1346  /* -------------- */
1347      pseudo_bit_t	reserved48[0x00020];
1348  /* -------------- */
1349      pseudo_bit_t	eq49_set_ci[0x00020];  /* EQ49_Set_CI */
1350  /* -------------- */
1351      pseudo_bit_t	reserved49[0x00020];
1352  /* -------------- */
1353      pseudo_bit_t	eq50_set_ci[0x00020];  /* EQ50_Set_CI */
1354  /* -------------- */
1355      pseudo_bit_t	reserved50[0x00020];
1356  /* -------------- */
1357      pseudo_bit_t	eq51_set_ci[0x00020];  /* EQ51_Set_CI */
1358  /* -------------- */
1359      pseudo_bit_t	reserved51[0x00020];
1360  /* -------------- */
1361      pseudo_bit_t	eq52_set_ci[0x00020];  /* EQ52_Set_CI */
1362  /* -------------- */
1363      pseudo_bit_t	reserved52[0x00020];
1364  /* -------------- */
1365      pseudo_bit_t	eq53_set_ci[0x00020];  /* EQ53_Set_CI */
1366  /* -------------- */
1367      pseudo_bit_t	reserved53[0x00020];
1368  /* -------------- */
1369      pseudo_bit_t	eq54_set_ci[0x00020];  /* EQ54_Set_CI */
1370  /* -------------- */
1371      pseudo_bit_t	reserved54[0x00020];
1372  /* -------------- */
1373      pseudo_bit_t	eq55_set_ci[0x00020];  /* EQ55_Set_CI */
1374  /* -------------- */
1375      pseudo_bit_t	reserved55[0x00020];
1376  /* -------------- */
1377      pseudo_bit_t	eq56_set_ci[0x00020];  /* EQ56_Set_CI */
1378  /* -------------- */
1379      pseudo_bit_t	reserved56[0x00020];
1380  /* -------------- */
1381      pseudo_bit_t	eq57_set_ci[0x00020];  /* EQ57_Set_CI */
1382  /* -------------- */
1383      pseudo_bit_t	reserved57[0x00020];
1384  /* -------------- */
1385      pseudo_bit_t	eq58_set_ci[0x00020];  /* EQ58_Set_CI */
1386  /* -------------- */
1387      pseudo_bit_t	reserved58[0x00020];
1388  /* -------------- */
1389      pseudo_bit_t	eq59_set_ci[0x00020];  /* EQ59_Set_CI */
1390  /* -------------- */
1391      pseudo_bit_t	reserved59[0x00020];
1392  /* -------------- */
1393      pseudo_bit_t	eq60_set_ci[0x00020];  /* EQ60_Set_CI */
1394  /* -------------- */
1395      pseudo_bit_t	reserved60[0x00020];
1396  /* -------------- */
1397      pseudo_bit_t	eq61_set_ci[0x00020];  /* EQ61_Set_CI */
1398  /* -------------- */
1399      pseudo_bit_t	reserved61[0x00020];
1400  /* -------------- */
1401      pseudo_bit_t	eq62_set_ci[0x00020];  /* EQ62_Set_CI */
1402  /* -------------- */
1403      pseudo_bit_t	reserved62[0x00020];
1404  /* -------------- */
1405      pseudo_bit_t	eq63_set_ci[0x00020];  /* EQ63_Set_CI */
1406  /* -------------- */
1407      pseudo_bit_t	reserved63[0x00020];
1408  /* -------------- */
1409  };
1410  
1411  /* InfiniHost-III-EX Configuration Registers */
1412  
1413  struct arbelprm_configuration_registers_st {	/* Little Endian */
1414      pseudo_bit_t	reserved0[0x403400];
1415  /* -------------- */
1416      struct arbelprm_hca_command_register_st	hca_command_interface_register;/* HCA Command Register */
1417  /* -------------- */
1418      pseudo_bit_t	reserved1[0x3fcb20];
1419  /* -------------- */
1420  };
1421  
1422  /* QP_DB_Record */
1423  
1424  struct arbelprm_qp_db_record_st {	/* Little Endian */
1425      pseudo_bit_t	counter[0x00010];      /* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */
1426      pseudo_bit_t	reserved0[0x00010];
1427  /* -------------- */
1428      pseudo_bit_t	reserved1[0x00005];
1429      pseudo_bit_t	res[0x00003];          /* 0x3 for SQ
1430                                                   0x4 for RQ
1431                                                   0x5 for SRQ */
1432      pseudo_bit_t	qp_number[0x00018];    /* QP number */
1433  /* -------------- */
1434  };
1435  
1436  /* CQ_ARM_DB_Record */
1437  
1438  struct arbelprm_cq_arm_db_record_st {	/* Little Endian */
1439      pseudo_bit_t	counter[0x00020];      /* CQ counter for the arming request */
1440  /* -------------- */
1441      pseudo_bit_t	cmd[0x00003];          /* 0x0 - No command
1442                                                   0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter.
1443                                                   0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter.
1444                                                   0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated
1445                                                   Other - Reserved */
1446      pseudo_bit_t	cmd_sn[0x00002];       /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */
1447      pseudo_bit_t	res[0x00003];          /* Must be 0x2 */
1448      pseudo_bit_t	cq_number[0x00018];    /* CQ number */
1449  /* -------------- */
1450  };
1451  
1452  /* CQ_CI_DB_Record */
1453  
1454  struct arbelprm_cq_ci_db_record_st {	/* Little Endian */
1455      pseudo_bit_t	counter[0x00020];      /* CQ counter */
1456  /* -------------- */
1457      pseudo_bit_t	reserved0[0x00005];
1458      pseudo_bit_t	res[0x00003];          /* Must be 0x1 */
1459      pseudo_bit_t	cq_number[0x00018];    /* CQ number */
1460  /* -------------- */
1461  };
1462  
1463  /* Virtual_Physical_Mapping */
1464  
1465  struct arbelprm_virtual_physical_mapping_st {	/* Little Endian */
1466      pseudo_bit_t	va_h[0x00020];         /* Virtual Address[63:32]. Valid only for MAP_ICM command. */
1467  /* -------------- */
1468      pseudo_bit_t	reserved0[0x0000c];
1469      pseudo_bit_t	va_l[0x00014];         /* Virtual Address[31:12]. Valid only for MAP_ICM command. */
1470  /* -------------- */
1471      pseudo_bit_t	pa_h[0x00020];         /* Physical Address[63:32] */
1472  /* -------------- */
1473      pseudo_bit_t	log2size[0x00006];     /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */
1474      pseudo_bit_t	reserved1[0x00006];
1475      pseudo_bit_t	pa_l[0x00014];         /* Physical Address[31:12] */
1476  /* -------------- */
1477  };
1478  
1479  /* MOD_STAT_CFG */
1480  
1481  struct arbelprm_mod_stat_cfg_st {	/* Little Endian */
1482      pseudo_bit_t	log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */
1483      pseudo_bit_t	reserved0[0x00001];
1484      pseudo_bit_t	srq[0x00001];          /* When set SRQs are supported */
1485      pseudo_bit_t	srq_m[0x00001];        /* Modify SRQ parameters */
1486      pseudo_bit_t	reserved1[0x00018];
1487  /* -------------- */
1488      pseudo_bit_t	reserved2[0x007e0];
1489  /* -------------- */
1490  };
1491  
1492  /* SRQ Context */
1493  
1494  struct arbelprm_srq_context_st {	/* Little Endian */
1495      pseudo_bit_t	srqn[0x00018];         /* SRQ number */
1496      pseudo_bit_t	log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue.
1497                                                   Maximum value is 0x10, i.e. 16M WQEs. */
1498      pseudo_bit_t	state[0x00004];        /* SRQ State:
1499                                                   1111 - SW Ownership
1500                                                   0000 - HW Ownership
1501                                                   0001 - Error
1502                                                   Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
1503  /* -------------- */
1504      pseudo_bit_t	l_key[0x00020];        /* memory key (L-Key) to be used to access WQEs. */
1505  /* -------------- */
1506      pseudo_bit_t	srq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
1507                                                   HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record.
1508                                                   The entry is obtained via the usr_page field. */
1509  /* -------------- */
1510      pseudo_bit_t	usr_page[0x00018];     /* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
1511      pseudo_bit_t	reserved0[0x00005];
1512      pseudo_bit_t	log_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
1513  /* -------------- */
1514      pseudo_bit_t	wqe_addr_h[0x00020];   /* Bits 63:32 of WQE address (WQE base address) */
1515  /* -------------- */
1516      pseudo_bit_t	reserved1[0x00006];
1517      pseudo_bit_t	srq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */
1518  /* -------------- */
1519      pseudo_bit_t	pd[0x00018];           /* SRQ protection domain. */
1520      pseudo_bit_t	reserved2[0x00008];
1521  /* -------------- */
1522      pseudo_bit_t	wqe_cnt[0x00010];      /* WQE count on the SRQ.
1523                                                   Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
1524      pseudo_bit_t	lwm[0x00010];          /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */
1525  /* -------------- */
1526      pseudo_bit_t	srq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
1527                                                   Must be 0x0 in SRQ initialization.
1528                                                   (QUERY_SRQ only). */
1529      pseudo_bit_t	reserved3[0x00010];
1530  /* -------------- */
1531      pseudo_bit_t	reserved4[0x00060];
1532  /* -------------- */
1533  };
1534  
1535  /* PBL */
1536  
1537  struct arbelprm_pbl_st {	/* Little Endian */
1538      pseudo_bit_t	mtt_0_h[0x00020];      /* First MTT[63:32] */
1539  /* -------------- */
1540      pseudo_bit_t	mtt_0_l[0x00020];      /* First MTT[31:0] */
1541  /* -------------- */
1542      pseudo_bit_t	mtt_1_h[0x00020];      /* Second MTT[63:32] */
1543  /* -------------- */
1544      pseudo_bit_t	mtt_1_l[0x00020];      /* Second MTT[31:0] */
1545  /* -------------- */
1546      pseudo_bit_t	mtt_2_h[0x00020];      /* Third MTT[63:32] */
1547  /* -------------- */
1548      pseudo_bit_t	mtt_2_l[0x00020];      /* Third MTT[31:0] */
1549  /* -------------- */
1550      pseudo_bit_t	mtt_3_h[0x00020];      /* Fourth MTT[63:32] */
1551  /* -------------- */
1552      pseudo_bit_t	mtt_3_l[0x00020];      /* Fourth MTT[31:0] */
1553  /* -------------- */
1554  };
1555  
1556  /* Performance Counters */
1557  
1558  struct arbelprm_performance_counters_st {	/* Little Endian */
1559      pseudo_bit_t	sqpc_access_cnt[0x00020];/* SQPC cache access count */
1560  /* -------------- */
1561      pseudo_bit_t	sqpc_miss_cnt[0x00020];/* SQPC cache miss count */
1562  /* -------------- */
1563      pseudo_bit_t	reserved0[0x00040];
1564  /* -------------- */
1565      pseudo_bit_t	rqpc_access_cnt[0x00020];/* RQPC cache access count */
1566  /* -------------- */
1567      pseudo_bit_t	rqpc_miss_cnt[0x00020];/* RQPC cache miss count */
1568  /* -------------- */
1569      pseudo_bit_t	reserved1[0x00040];
1570  /* -------------- */
1571      pseudo_bit_t	cqc_access_cnt[0x00020];/* CQC cache access count */
1572  /* -------------- */
1573      pseudo_bit_t	cqc_miss_cnt[0x00020]; /* CQC cache miss count */
1574  /* -------------- */
1575      pseudo_bit_t	reserved2[0x00040];
1576  /* -------------- */
1577      pseudo_bit_t	tpt_access_cnt[0x00020];/* TPT cache access count */
1578  /* -------------- */
1579      pseudo_bit_t	mpt_miss_cnt[0x00020]; /* MPT cache miss count */
1580  /* -------------- */
1581      pseudo_bit_t	mtt_miss_cnt[0x00020]; /* MTT cache miss count */
1582  /* -------------- */
1583      pseudo_bit_t	reserved3[0x00620];
1584  /* -------------- */
1585  };
1586  
1587  /* Transport and CI Error Counters */
1588  
1589  struct arbelprm_transport_and_ci_error_counters_st {	/* Little Endian */
1590      pseudo_bit_t	rq_num_lle[0x00020];   /* Responder - number of local length errors */
1591  /* -------------- */
1592      pseudo_bit_t	sq_num_lle[0x00020];   /* Requester - number of local length errors */
1593  /* -------------- */
1594      pseudo_bit_t	rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */
1595  /* -------------- */
1596      pseudo_bit_t	sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */
1597  /* -------------- */
1598      pseudo_bit_t	rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */
1599  /* -------------- */
1600      pseudo_bit_t	sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */
1601  /* -------------- */
1602      pseudo_bit_t	rq_num_lpe[0x00020];   /* Responder - number of local protection errors */
1603  /* -------------- */
1604      pseudo_bit_t	sq_num_lpe[0x00020];   /* Requester - number of local protection errors */
1605  /* -------------- */
1606      pseudo_bit_t	rq_num_wrfe[0x00020];  /* Responder - number of CQEs with error.
1607                                                   Incremented each time a CQE with error is generated */
1608  /* -------------- */
1609      pseudo_bit_t	sq_num_wrfe[0x00020];  /* Requester - number of CQEs with error.
1610                                                   Incremented each time a CQE with error is generated */
1611  /* -------------- */
1612      pseudo_bit_t	reserved0[0x00020];
1613  /* -------------- */
1614      pseudo_bit_t	sq_num_mwbe[0x00020];  /* Requester - number of memory window bind errors */
1615  /* -------------- */
1616      pseudo_bit_t	reserved1[0x00020];
1617  /* -------------- */
1618      pseudo_bit_t	sq_num_bre[0x00020];   /* Requester - number of bad response errors */
1619  /* -------------- */
1620      pseudo_bit_t	rq_num_lae[0x00020];   /* Responder - number of local access errors */
1621  /* -------------- */
1622      pseudo_bit_t	reserved2[0x00040];
1623  /* -------------- */
1624      pseudo_bit_t	sq_num_rire[0x00020];  /* Requester - number of remote invalid request errors
1625                                                   NAK-Invalid Request on:
1626                                                   1. Unsupported OpCode: Responder detected an unsupported OpCode.
1627                                                   2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such
1628                                                   as a missing "Last" packet.
1629                                                   Note: there is no PSN error, thus this does not indicate a dropped packet. */
1630  /* -------------- */
1631      pseudo_bit_t	rq_num_rire[0x00020];  /* Responder - number of remote invalid request errors.
1632                                                   NAK may or may not be sent.
1633                                                   1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only):
1634                                                   Inbound request OpCode was either reserved, or was for a function not supported by this
1635                                                   QP. (E.g. RDMA or ATOMIC on QP not set up for this).
1636                                                   2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion.
1637                                                   3. Too many RDMA READ or ATOMIC Requests: There were more requests received
1638                                                   and not ACKed than allowed for the connection.
1639                                                   4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder
1640                                                   detected an error in the sequence of OpCodes; a missing "Last" packet
1641                                                   5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder
1642                                                   detected an error in the sequence of OpCodes; a missing "First" packet
1643                                                   6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able
1644                                                   buffer space.
1645                                                   7. Length error: RDMA WRITE request message contained too much or too little pay-load
1646                                                   data compared to the DMA length advertised in the first or only packet.
1647                                                   8. Length error: Payload length was not consistent with the opcode:
1648                                                   a: 0 byte <= "only" <= PMTU bytes
1649                                                   b: ("first" or "middle") == PMTU bytes
1650                                                   c: 1byte <= "last" <= PMTU bytes
1651                                                   9. Length error: Inbound message exceeded the size supported by the CA port. */
1652  /* -------------- */
1653      pseudo_bit_t	sq_num_rae[0x00020];   /* Requester - number of remote access errors.
1654                                                   NAK-Remote Access Error on:
1655                                                   R_Key Violation: Responder detected an invalid R_Key while executing an RDMA
1656                                                   Request. */
1657  /* -------------- */
1658      pseudo_bit_t	rq_num_rae[0x00020];   /* Responder - number of remote access errors.
1659                                                   R_Key Violation Responder detected an R_Key violation while executing an RDMA
1660                                                   request.
1661                                                   NAK may or may not be sent. */
1662  /* -------------- */
1663      pseudo_bit_t	sq_num_roe[0x00020];   /* Requester - number of remote operation errors.
1664                                                   NAK-Remote Operation Error on:
1665                                                   Remote Operation Error: Responder encountered an error, (local to the responder),
1666                                                   which prevented it from completing the request. */
1667  /* -------------- */
1668      pseudo_bit_t	rq_num_roe[0x00020];   /* Responder - number of remote operation errors.
1669                                                   NAK-Remote Operation Error on:
1670                                                   1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing
1671                                                   the packet.
1672                                                   2. Remote Operation Error: Responder encountered an error, (local to the responder),
1673                                                   which prevented it from completing the request. */
1674  /* -------------- */
1675      pseudo_bit_t	sq_num_tree[0x00020];  /* Requester - number of transport retries exceeded errors */
1676  /* -------------- */
1677      pseudo_bit_t	reserved3[0x00020];
1678  /* -------------- */
1679      pseudo_bit_t	sq_num_rree[0x00020];  /* Requester - number of RNR nak retries exceeded errors */
1680  /* -------------- */
1681      pseudo_bit_t	reserved4[0x00020];
1682  /* -------------- */
1683      pseudo_bit_t	sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */
1684  /* -------------- */
1685      pseudo_bit_t	rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */
1686  /* -------------- */
1687      pseudo_bit_t	reserved5[0x00040];
1688  /* -------------- */
1689      pseudo_bit_t	sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */
1690  /* -------------- */
1691      pseudo_bit_t	reserved6[0x00020];
1692  /* -------------- */
1693      pseudo_bit_t	sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */
1694  /* -------------- */
1695      pseudo_bit_t	reserved7[0x00020];
1696  /* -------------- */
1697      pseudo_bit_t	sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */
1698  /* -------------- */
1699      pseudo_bit_t	reserved8[0x00380];
1700  /* -------------- */
1701      pseudo_bit_t	rq_num_oos[0x00020];   /* Responder - number of out of sequence requests received */
1702  /* -------------- */
1703      pseudo_bit_t	sq_num_oos[0x00020];   /* Requester - number of out of sequence Naks received */
1704  /* -------------- */
1705      pseudo_bit_t	rq_num_mce[0x00020];   /* Responder - number of bad multicast packets received */
1706  /* -------------- */
1707      pseudo_bit_t	reserved9[0x00020];
1708  /* -------------- */
1709      pseudo_bit_t	rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */
1710  /* -------------- */
1711      pseudo_bit_t	sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */
1712  /* -------------- */
1713      pseudo_bit_t	rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */
1714  /* -------------- */
1715      pseudo_bit_t	reserved10[0x00020];
1716  /* -------------- */
1717      pseudo_bit_t	rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */
1718  /* -------------- */
1719      pseudo_bit_t	reserved11[0x003e0];
1720  /* -------------- */
1721      pseudo_bit_t	num_cqovf[0x00020];    /* Number of CQ overflows */
1722  /* -------------- */
1723      pseudo_bit_t	num_eqovf[0x00020];    /* Number of EQ overflows */
1724  /* -------------- */
1725      pseudo_bit_t	num_baddb[0x00020];    /* Number of bad doorbells */
1726  /* -------------- */
1727      pseudo_bit_t	reserved12[0x002a0];
1728  /* -------------- */
1729  };
1730  
1731  /* Event_data Field - HCR Completion Event */
1732  
1733  struct arbelprm_hcr_completion_event_st {	/* Little Endian */
1734      pseudo_bit_t	token[0x00010];        /* HCR Token */
1735      pseudo_bit_t	reserved0[0x00010];
1736  /* -------------- */
1737      pseudo_bit_t	reserved1[0x00020];
1738  /* -------------- */
1739      pseudo_bit_t	status[0x00008];       /* HCR Status */
1740      pseudo_bit_t	reserved2[0x00018];
1741  /* -------------- */
1742      pseudo_bit_t	out_param_h[0x00020];  /* HCR Output Parameter [63:32] */
1743  /* -------------- */
1744      pseudo_bit_t	out_param_l[0x00020];  /* HCR Output Parameter [31:0] */
1745  /* -------------- */
1746      pseudo_bit_t	reserved3[0x00020];
1747  /* -------------- */
1748  };
1749  
1750  /* Completion with Error CQE */
1751  
1752  struct arbelprm_completion_with_error_st {	/* Little Endian */
1753      pseudo_bit_t	myqpn[0x00018];        /* Indicates the QP for which completion is being reported */
1754      pseudo_bit_t	reserved0[0x00008];
1755  /* -------------- */
1756      pseudo_bit_t	reserved1[0x00060];
1757  /* -------------- */
1758      pseudo_bit_t	reserved2[0x00010];
1759      pseudo_bit_t	vendor_code[0x00008];
1760      pseudo_bit_t	syndrome[0x00008];     /* Completion with error syndrome:
1761                                                           0x01 - Local Length Error
1762                                                           0x02 - Local QP Operation Error
1763                                                           0x03 - Local EE Context Operation Error
1764                                                           0x04 - Local Protection Error
1765                                                           0x05 - Work Request Flushed Error
1766                                                           0x06 - Memory Window Bind Error
1767                                                           0x10 - Bad Response Error
1768                                                           0x11 - Local Access Error
1769                                                           0x12 - Remote Invalid Request Error
1770                                                           0x13 - Remote Access Error
1771                                                           0x14 - Remote Operation Error
1772                                                           0x15 - Transport Retry Counter Exceeded
1773                                                           0x16 - RNR Retry Counter Exceeded
1774                                                           0x20 - Local RDD Violation Error
1775                                                           0x21 - Remote Invalid RD Request
1776                                                           0x22 - Remote Aborted Error
1777                                                           0x23 - Invalid EE Context Number
1778                                                           0x24 - Invalid EE Context State
1779                                                           other - Reserved
1780                                                   Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
1781  /* -------------- */
1782      pseudo_bit_t	reserved3[0x00020];
1783  /* -------------- */
1784      pseudo_bit_t	reserved4[0x00006];
1785      pseudo_bit_t	wqe_addr[0x0001a];     /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
1786  /* -------------- */
1787      pseudo_bit_t	reserved5[0x00007];
1788      pseudo_bit_t	owner[0x00001];        /* Owner field. Zero value of this field means SW ownership of CQE. */
1789      pseudo_bit_t	reserved6[0x00010];
1790      pseudo_bit_t	opcode[0x00008];       /* The opcode of WQE completion is reported for.
1791  
1792                                                   The following values are reported in case of completion with error:
1793                                                   0xFE - For completion with error on Receive Queues
1794                                                   0xFF - For completion with error on Send Queues */
1795  /* -------------- */
1796  };
1797  
1798  /* Resize CQ Input Mailbox */
1799  
1800  struct arbelprm_resize_cq_st {	/* Little Endian */
1801      pseudo_bit_t	reserved0[0x00020];
1802  /* -------------- */
1803      pseudo_bit_t	start_addr_h[0x00020]; /* Start address of CQ[63:32].
1804                                                   Must be aligned on CQE size (32 bytes) */
1805  /* -------------- */
1806      pseudo_bit_t	start_addr_l[0x00020]; /* Start address of CQ[31:0].
1807                                                   Must be aligned on CQE size (32 bytes) */
1808  /* -------------- */
1809      pseudo_bit_t	reserved1[0x00018];
1810      pseudo_bit_t	log_cq_size[0x00005];  /* Log (base 2) of the CQ size (in entries) */
1811      pseudo_bit_t	reserved2[0x00003];
1812  /* -------------- */
1813      pseudo_bit_t	reserved3[0x00060];
1814  /* -------------- */
1815      pseudo_bit_t	l_key[0x00020];        /* Memory key (L_Key) to be used to access CQ */
1816  /* -------------- */
1817      pseudo_bit_t	reserved4[0x00100];
1818  /* -------------- */
1819  };
1820  
1821  /* MAD_IFC Input Modifier */
1822  
1823  struct arbelprm_mad_ifc_input_modifier_st {	/* Little Endian */
1824      pseudo_bit_t	port_number[0x00008];  /* The packet reception port number (1 or 2). */
1825      pseudo_bit_t	mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
1826                                                   Required for trap generation when BKey check is enabled and for global routed packets. */
1827      pseudo_bit_t	reserved0[0x00007];
1828      pseudo_bit_t	rlid[0x00010];         /* Remote (source) LID  from the received MAD.
1829                                                   This field is required for trap generation upon MKey/BKey validation. */
1830  /* -------------- */
1831  };
1832  
1833  /* MAD_IFC Input Mailbox */
1834  
1835  struct arbelprm_mad_ifc_st {	/* Little Endian */
1836      pseudo_bit_t	request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */
1837  /* -------------- */
1838      pseudo_bit_t	my_qpn[0x00018];       /* Destination QP number from the received MAD.
1839                                                   This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1840      pseudo_bit_t	reserved0[0x00008];
1841  /* -------------- */
1842      pseudo_bit_t	rqpn[0x00018];         /* Remote (source) QP number  from the received MAD.
1843                                                   This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1844      pseudo_bit_t	reserved1[0x00008];
1845  /* -------------- */
1846      pseudo_bit_t	rlid[0x00010];         /* Remote (source) LID  from the received MAD.
1847                                                   This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1848      pseudo_bit_t	ml_path[0x00007];      /* My (destination) LID path bits  from the received MAD.
1849                                                   This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1850      pseudo_bit_t	g[0x00001];            /* If set, the GRH field in valid.
1851                                                   This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1852      pseudo_bit_t	reserved2[0x00004];
1853      pseudo_bit_t	sl[0x00004];           /* Service Level of the received MAD.
1854                                                   This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1855  /* -------------- */
1856      pseudo_bit_t	pkey_indx[0x00010];    /* Index in PKey table that matches PKey of the received MAD.
1857                                                   This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1858      pseudo_bit_t	reserved3[0x00010];
1859  /* -------------- */
1860      pseudo_bit_t	reserved4[0x00180];
1861  /* -------------- */
1862      pseudo_bit_t	grh[10][0x00020];      /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list.
1863                                                   Valid if Mad_extended_info bit (in the input modifier) and g bit are set.
1864                                                   Otherwise this field is reserved. */
1865  /* -------------- */
1866      pseudo_bit_t	reserved5[0x004c0];
1867  /* -------------- */
1868  };
1869  
1870  /* Query Debug Message */
1871  
1872  struct arbelprm_query_debug_msg_st {	/* Little Endian */
1873      pseudo_bit_t	phy_addr_h[0x00020];   /* Translation of the address in firmware area. High 32 bits. */
1874  /* -------------- */
1875      pseudo_bit_t	v[0x00001];            /* Physical translation is valid */
1876      pseudo_bit_t	reserved0[0x0000b];
1877      pseudo_bit_t	phy_addr_l[0x00014];   /* Translation of the address in firmware area. Low 32 bits. */
1878  /* -------------- */
1879      pseudo_bit_t	fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
1880  /* -------------- */
1881      pseudo_bit_t	fw_area_size[0x00020]; /* Firmware area size */
1882  /* -------------- */
1883      pseudo_bit_t	trc_hdr_sz[0x00020];   /* Trace message header size in dwords. */
1884  /* -------------- */
1885      pseudo_bit_t	trc_arg_num[0x00020];  /* The number of arguments per trace message. */
1886  /* -------------- */
1887      pseudo_bit_t	reserved1[0x000c0];
1888  /* -------------- */
1889      pseudo_bit_t	dbg_msk_h[0x00020];    /* Debug messages mask [63:32] */
1890  /* -------------- */
1891      pseudo_bit_t	dbg_msk_l[0x00020];    /* Debug messages mask [31:0] */
1892  /* -------------- */
1893      pseudo_bit_t	reserved2[0x00040];
1894  /* -------------- */
1895      pseudo_bit_t	buff0_addr[0x00020];   /* Address in firmware area of Trace Buffer 0 */
1896  /* -------------- */
1897      pseudo_bit_t	buff0_size[0x00020];   /* Size of Trace Buffer 0 */
1898  /* -------------- */
1899      pseudo_bit_t	buff1_addr[0x00020];   /* Address in firmware area of Trace Buffer 1 */
1900  /* -------------- */
1901      pseudo_bit_t	buff1_size[0x00020];   /* Size of Trace Buffer 1 */
1902  /* -------------- */
1903      pseudo_bit_t	buff2_addr[0x00020];   /* Address in firmware area of Trace Buffer 2 */
1904  /* -------------- */
1905      pseudo_bit_t	buff2_size[0x00020];   /* Size of Trace Buffer 2 */
1906  /* -------------- */
1907      pseudo_bit_t	buff3_addr[0x00020];   /* Address in firmware area of Trace Buffer 3 */
1908  /* -------------- */
1909      pseudo_bit_t	buff3_size[0x00020];   /* Size of Trace Buffer 3 */
1910  /* -------------- */
1911      pseudo_bit_t	buff4_addr[0x00020];   /* Address in firmware area of Trace Buffer 4 */
1912  /* -------------- */
1913      pseudo_bit_t	buff4_size[0x00020];   /* Size of Trace Buffer 4 */
1914  /* -------------- */
1915      pseudo_bit_t	buff5_addr[0x00020];   /* Address in firmware area of Trace Buffer 5 */
1916  /* -------------- */
1917      pseudo_bit_t	buff5_size[0x00020];   /* Size of Trace Buffer 5 */
1918  /* -------------- */
1919      pseudo_bit_t	buff6_addr[0x00020];   /* Address in firmware area of Trace Buffer 6 */
1920  /* -------------- */
1921      pseudo_bit_t	buff6_size[0x00020];   /* Size of Trace Buffer 6 */
1922  /* -------------- */
1923      pseudo_bit_t	buff7_addr[0x00020];   /* Address in firmware area of Trace Buffer 7 */
1924  /* -------------- */
1925      pseudo_bit_t	buff7_size[0x00020];   /* Size of Trace Buffer 7 */
1926  /* -------------- */
1927      pseudo_bit_t	reserved3[0x00400];
1928  /* -------------- */
1929  };
1930  
1931  /* User Access Region */
1932  
1933  struct arbelprm_uar_st {	/* Little Endian */
1934      struct arbelprm_rd_send_doorbell_st	rd_send_doorbell;/* Reliable Datagram send doorbell */
1935  /* -------------- */
1936      struct arbelprm_send_doorbell_st	send_doorbell;/* Send doorbell */
1937  /* -------------- */
1938      pseudo_bit_t	reserved0[0x00040];
1939  /* -------------- */
1940      struct arbelprm_cq_cmd_doorbell_st	cq_command_doorbell;/* CQ Doorbell */
1941  /* -------------- */
1942      pseudo_bit_t	reserved1[0x03ec0];
1943  /* -------------- */
1944  };
1945  
1946  /* Receive doorbell */
1947  
1948  struct arbelprm_receive_doorbell_st {	/* Little Endian */
1949      pseudo_bit_t	reserved0[0x00008];
1950      pseudo_bit_t	wqe_counter[0x00010];  /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
1951      pseudo_bit_t	reserved1[0x00008];
1952  /* -------------- */
1953      pseudo_bit_t	reserved2[0x00005];
1954      pseudo_bit_t	srq[0x00001];          /* If set, this is a Shared Receive Queue */
1955      pseudo_bit_t	reserved3[0x00002];
1956      pseudo_bit_t	qpn[0x00018];          /* QP number or SRQ number this doorbell is rung on */
1957  /* -------------- */
1958  };
1959  
1960  /* SET_IB Parameters */
1961  
1962  struct arbelprm_set_ib_st {	/* Little Endian */
1963      pseudo_bit_t	rqk[0x00001];          /* Reset QKey Violation Counter */
1964      pseudo_bit_t	reserved0[0x00011];
1965      pseudo_bit_t	sig[0x00001];          /* Set System Image GUID to system_image_guid specified.
1966                                                   system_image_guid and sig must be the same for all ports. */
1967      pseudo_bit_t	reserved1[0x0000d];
1968  /* -------------- */
1969      pseudo_bit_t	capability_mask[0x00020];/* PortInfo Capability Mask */
1970  /* -------------- */
1971      pseudo_bit_t	system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
1972                                                   Must be the same for both ports. */
1973  /* -------------- */
1974      pseudo_bit_t	system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
1975                                                   Must be the same for both ports. */
1976  /* -------------- */
1977      pseudo_bit_t	reserved2[0x00180];
1978  /* -------------- */
1979  };
1980  
1981  /* Multicast Group Member */
1982  
1983  struct arbelprm_mgm_entry_st {	/* Little Endian */
1984      pseudo_bit_t	reserved0[0x00006];
1985      pseudo_bit_t	next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.
1986                                                   The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.
1987                                                   next_gid_index=0 means end of the chain. */
1988  /* -------------- */
1989      pseudo_bit_t	reserved1[0x00060];
1990  /* -------------- */
1991      pseudo_bit_t	mgid_128_96[0x00020];  /* Multicast group GID[128:96] in big endian format.
1992                                                   Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1993  /* -------------- */
1994      pseudo_bit_t	mgid_95_64[0x00020];   /* Multicast group GID[95:64] in big endian format.
1995                                                   Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1996  /* -------------- */
1997      pseudo_bit_t	mgid_63_32[0x00020];   /* Multicast group GID[63:32] in big endian format.
1998                                                   Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1999  /* -------------- */
2000      pseudo_bit_t	mgid_31_0[0x00020];    /* Multicast group GID[31:0] in big endian format.
2001                                                   Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
2002  /* -------------- */
2003      struct arbelprm_mgmqp_st	mgmqp_0;   /* Multicast Group Member QP */
2004  /* -------------- */
2005      struct arbelprm_mgmqp_st	mgmqp_1;   /* Multicast Group Member QP */
2006  /* -------------- */
2007      struct arbelprm_mgmqp_st	mgmqp_2;   /* Multicast Group Member QP */
2008  /* -------------- */
2009      struct arbelprm_mgmqp_st	mgmqp_3;   /* Multicast Group Member QP */
2010  /* -------------- */
2011      struct arbelprm_mgmqp_st	mgmqp_4;   /* Multicast Group Member QP */
2012  /* -------------- */
2013      struct arbelprm_mgmqp_st	mgmqp_5;   /* Multicast Group Member QP */
2014  /* -------------- */
2015      struct arbelprm_mgmqp_st	mgmqp_6;   /* Multicast Group Member QP */
2016  /* -------------- */
2017      struct arbelprm_mgmqp_st	mgmqp_7;   /* Multicast Group Member QP */
2018  /* -------------- */
2019  };
2020  
2021  /* INIT_IB Parameters */
2022  
2023  struct arbelprm_init_ib_st {	/* Little Endian */
2024      pseudo_bit_t	reserved0[0x00004];
2025      pseudo_bit_t	vl_cap[0x00004];       /* Maximum VLs supported on the port, excluding VL15.
2026                                                   Legal values are 1,2,4 and 8. */
2027      pseudo_bit_t	port_width_cap[0x00004];/* IB Port Width
2028                                                   1   - 1x
2029                                                   3   - 1x, 4x
2030                                                   11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208)
2031                                                   else - Reserved */
2032      pseudo_bit_t	mtu_cap[0x00004];      /* Maximum MTU Supported
2033                                                   0x0 - Reserved
2034                                                   0x1 - 256
2035                                                   0x2 - 512
2036                                                   0x3 - 1024
2037                                                   0x4 - 2048
2038                                                   0x5 - 0xF Reserved */
2039      pseudo_bit_t	g0[0x00001];           /* Set port GUID0 to GUID0 specified */
2040      pseudo_bit_t	ng[0x00001];           /* Set node GUID to node_guid specified.
2041                                                   node_guid and ng must be the same for all ports. */
2042      pseudo_bit_t	sig[0x00001];          /* Set System Image GUID to system_image_guid specified.
2043                                                   system_image_guid and sig must be the same for all ports. */
2044      pseudo_bit_t	reserved1[0x0000d];
2045  /* -------------- */
2046      pseudo_bit_t	max_gid[0x00010];      /* Maximum number of GIDs for the port */
2047      pseudo_bit_t	reserved2[0x00010];
2048  /* -------------- */
2049      pseudo_bit_t	max_pkey[0x00010];     /* Maximum pkeys for the port.
2050                                                   Must be the same for both ports. */
2051      pseudo_bit_t	reserved3[0x00010];
2052  /* -------------- */
2053      pseudo_bit_t	reserved4[0x00020];
2054  /* -------------- */
2055      pseudo_bit_t	guid0_h[0x00020];      /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */
2056  /* -------------- */
2057      pseudo_bit_t	guid0_l[0x00020];      /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */
2058  /* -------------- */
2059      pseudo_bit_t	node_guid_h[0x00020];  /* Node GUID[63:32], takes effect only if the NG bit is set
2060                                                   Must be the same for both ports. */
2061  /* -------------- */
2062      pseudo_bit_t	node_guid_l[0x00020];  /* Node GUID[31:0], takes effect only if the NG bit is set
2063                                                   Must be the same for both ports. */
2064  /* -------------- */
2065      pseudo_bit_t	system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
2066                                                   Must be the same for both ports. */
2067  /* -------------- */
2068      pseudo_bit_t	system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
2069                                                   Must be the same for both ports. */
2070  /* -------------- */
2071      pseudo_bit_t	reserved5[0x006c0];
2072  /* -------------- */
2073  };
2074  
2075  /* Query Device Limitations */
2076  
2077  struct arbelprm_query_dev_lim_st {	/* Little Endian */
2078      pseudo_bit_t	reserved0[0x00080];
2079  /* -------------- */
2080      pseudo_bit_t	log_max_qp[0x00005];   /* Log2 of the Maximum number of QPs supported */
2081      pseudo_bit_t	reserved1[0x00003];
2082      pseudo_bit_t	log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
2083                                                   The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
2084      pseudo_bit_t	reserved2[0x00004];
2085      pseudo_bit_t	log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
2086      pseudo_bit_t	log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
2087  /* -------------- */
2088      pseudo_bit_t	log_max_ee[0x00005];   /* Log2 of the Maximum number of EE contexts supported */
2089      pseudo_bit_t	reserved3[0x00003];
2090      pseudo_bit_t	log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use
2091                                                   The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */
2092      pseudo_bit_t	reserved4[0x00004];
2093      pseudo_bit_t	log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set.
2094                                                    */
2095      pseudo_bit_t	reserved5[0x00007];
2096      pseudo_bit_t	log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use
2097                                                   The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1
2098                                                   This parameter is valid only if the SRQ bit is set. */
2099  /* -------------- */
2100      pseudo_bit_t	log_max_cq[0x00005];   /* Log2 of the Maximum number of CQs supported */
2101      pseudo_bit_t	reserved6[0x00003];
2102      pseudo_bit_t	log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
2103                                                   The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
2104      pseudo_bit_t	reserved7[0x00004];
2105      pseudo_bit_t	log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
2106      pseudo_bit_t	reserved8[0x00008];
2107  /* -------------- */
2108      pseudo_bit_t	log_max_eq[0x00003];   /* Log2 of the Maximum number of EQs */
2109      pseudo_bit_t	reserved9[0x00005];
2110      pseudo_bit_t	num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use
2111                                                   The reserved resources are numbered from 0 to num_rsvd_eqs-1
2112                                                   If 0 - no resources are reserved. */
2113      pseudo_bit_t	reserved10[0x00004];
2114      pseudo_bit_t	log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */
2115      pseudo_bit_t	reserved11[0x00002];
2116      pseudo_bit_t	log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */
2117  /* -------------- */
2118      pseudo_bit_t	log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */
2119      pseudo_bit_t	reserved12[0x00002];
2120      pseudo_bit_t	log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
2121                                                   The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
2122      pseudo_bit_t	reserved13[0x00004];
2123      pseudo_bit_t	log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */
2124      pseudo_bit_t	reserved14[0x00004];
2125      pseudo_bit_t	log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use
2126                                                   The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
2127                                                    */
2128  /* -------------- */
2129      pseudo_bit_t	reserved15[0x00020];
2130  /* -------------- */
2131      pseudo_bit_t	log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
2132      pseudo_bit_t	reserved16[0x0000a];
2133      pseudo_bit_t	log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
2134      pseudo_bit_t	reserved17[0x0000a];
2135  /* -------------- */
2136      pseudo_bit_t	log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
2137      pseudo_bit_t	reserved18[0x00016];
2138      pseudo_bit_t	log2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use
2139                                                   The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */
2140  /* -------------- */
2141      pseudo_bit_t	rsz_srq[0x00001];      /* Ability to modify the maximum number of WRs per SRQ. */
2142      pseudo_bit_t	reserved19[0x0001f];
2143  /* -------------- */
2144      pseudo_bit_t	num_ports[0x00004];    /* Number of IB ports. */
2145      pseudo_bit_t	max_vl[0x00004];       /* Maximum VLs supported on each port, excluding VL15 */
2146      pseudo_bit_t	max_port_width[0x00004];/* IB Port Width
2147                                                   1   - 1x
2148                                                   3   - 1x, 4x
2149                                                   11 - 1x, 4x or 12x
2150                                                   else - Reserved */
2151      pseudo_bit_t	max_mtu[0x00004];      /* Maximum MTU Supported
2152                                                   0x0 - Reserved
2153                                                   0x1 - 256
2154                                                   0x2 - 512
2155                                                   0x3 - 1024
2156                                                   0x4 - 2048
2157                                                   0x5 - 0xF Reserved */
2158      pseudo_bit_t	local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
2159                                                   The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */
2160      pseudo_bit_t	reserved20[0x0000b];
2161  /* -------------- */
2162      pseudo_bit_t	log_max_gid[0x00004];  /* Log2 of the maximum number of GIDs per port */
2163      pseudo_bit_t	reserved21[0x0001c];
2164  /* -------------- */
2165      pseudo_bit_t	log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */
2166      pseudo_bit_t	reserved22[0x0000c];
2167      pseudo_bit_t	stat_rate_support[0x00010];/* bit mask of stat rate supported
2168                                                   bit 0 - full bw
2169                                                   bit 1 - 1/4 bw
2170                                                   bit 2 - 1/8 bw
2171                                                   bit 3 - 1/2 bw; */
2172  /* -------------- */
2173      pseudo_bit_t	reserved23[0x00020];
2174  /* -------------- */
2175      pseudo_bit_t	rc[0x00001];           /* RC Transport supported */
2176      pseudo_bit_t	uc[0x00001];           /* UC Transport Supported */
2177      pseudo_bit_t	ud[0x00001];           /* UD Transport Supported */
2178      pseudo_bit_t	rd[0x00001];           /* RD Transport Supported */
2179      pseudo_bit_t	raw_ipv6[0x00001];     /* Raw IPv6 Transport Supported */
2180      pseudo_bit_t	raw_ether[0x00001];    /* Raw Ethertype Transport Supported */
2181      pseudo_bit_t	srq[0x00001];          /* SRQ is supported
2182                                                    */
2183      pseudo_bit_t	ipo_ib_checksum[0x00001];/* IP over IB checksum is supported */
2184      pseudo_bit_t	pkv[0x00001];          /* PKey Violation Counter Supported */
2185      pseudo_bit_t	qkv[0x00001];          /* QKey Violation Coutner Supported */
2186      pseudo_bit_t	reserved24[0x00006];
2187      pseudo_bit_t	mw[0x00001];           /* Memory windows supported */
2188      pseudo_bit_t	apm[0x00001];          /* Automatic Path Migration Supported */
2189      pseudo_bit_t	atm[0x00001];          /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */
2190      pseudo_bit_t	rm[0x00001];           /* Raw Multicast Supported */
2191      pseudo_bit_t	avp[0x00001];          /* Address Vector Port checking supported */
2192      pseudo_bit_t	udm[0x00001];          /* UD Multicast Supported */
2193      pseudo_bit_t	reserved25[0x00002];
2194      pseudo_bit_t	pg[0x00001];           /* Paging on demand supported */
2195      pseudo_bit_t	r[0x00001];            /* Router mode supported */
2196      pseudo_bit_t	reserved26[0x00006];
2197  /* -------------- */
2198      pseudo_bit_t	log_pg_sz[0x00008];    /* Minimum system page size supported (log2).
2199                                                   For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */
2200      pseudo_bit_t	reserved27[0x00008];
2201      pseudo_bit_t	uar_sz[0x00006];       /* UAR Area Size = 1MB * 2^uar_sz */
2202      pseudo_bit_t	reserved28[0x00006];
2203      pseudo_bit_t	num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use
2204                                                   The reserved resources are numbered from 0 to num_reserved_uars-1
2205                                                   Note that UAR number num_reserved_uars is always for the kernel. */
2206  /* -------------- */
2207      pseudo_bit_t	reserved29[0x00020];
2208  /* -------------- */
2209      pseudo_bit_t	max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */
2210      pseudo_bit_t	max_sg_sq[0x00008];    /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */
2211      pseudo_bit_t	reserved30[0x00008];
2212  /* -------------- */
2213      pseudo_bit_t	max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */
2214      pseudo_bit_t	max_sg_rq[0x00008];    /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */
2215      pseudo_bit_t	reserved31[0x00008];
2216  /* -------------- */
2217      pseudo_bit_t	reserved32[0x00040];
2218  /* -------------- */
2219      pseudo_bit_t	log_max_mcg[0x00008];  /* Log2 of the maximum number of multicast groups */
2220      pseudo_bit_t	num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
2221                                                   The reserved resources are numbered from 0 to num_reserved_mcgs-1
2222                                                   If 0 - no resources are reserved. */
2223      pseudo_bit_t	reserved33[0x00004];
2224      pseudo_bit_t	log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */
2225      pseudo_bit_t	reserved34[0x00008];
2226  /* -------------- */
2227      pseudo_bit_t	log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */
2228      pseudo_bit_t	reserved35[0x00006];
2229      pseudo_bit_t	num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use
2230                                                   The reserved resources are numbered from 0 to num_reserved_rdds-1.
2231                                                   If 0 - no resources are reserved. */
2232      pseudo_bit_t	log_max_pd[0x00006];   /* Log2 of the maximum number of PDs */
2233      pseudo_bit_t	reserved36[0x00006];
2234      pseudo_bit_t	num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use
2235                                                   The reserved resources are numbered from 0 to num_reserved_pds-1
2236                                                   If 0 - no resources are reserved. */
2237  /* -------------- */
2238      pseudo_bit_t	reserved37[0x000c0];
2239  /* -------------- */
2240      pseudo_bit_t	qpc_entry_sz[0x00010]; /* QPC Entry Size for the device
2241                                                   For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2242      pseudo_bit_t	eec_entry_sz[0x00010]; /* EEC Entry Size for the device
2243                                                   For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2244  /* -------------- */
2245      pseudo_bit_t	eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device
2246                                                   For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2247      pseudo_bit_t	eeec_entry_sz[0x00010];/* Extended EEC entry size for the device
2248                                                   For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2249  /* -------------- */
2250      pseudo_bit_t	cqc_entry_sz[0x00010]; /* CQC entry size for the device
2251                                                   For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2252      pseudo_bit_t	eqc_entry_sz[0x00010]; /* EQ context entry size for the device
2253                                                   For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2254  /* -------------- */
2255      pseudo_bit_t	uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size
2256                                                   For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2257      pseudo_bit_t	srq_entry_sz[0x00010]; /* SRQ context entry size for the device
2258                                                   For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2259  /* -------------- */
2260      pseudo_bit_t	mpt_entry_sz[0x00010]; /* MPT entry size in Bytes for the device.
2261                                                   For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2262      pseudo_bit_t	mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device.
2263                                                   For the InfiniHost-III-EX MT25208 entry size is 8 bytes */
2264  /* -------------- */
2265      pseudo_bit_t	bmme[0x00001];         /* Base Memory Management Extension Support */
2266      pseudo_bit_t	win_type[0x00001];     /* Bound Type 2 Memory Window Association mechanism:
2267                                                   0 - Type 2A - QP Number Association; or
2268                                                   1 - Type 2B - QP Number and PD Association. */
2269      pseudo_bit_t	mps[0x00001];          /* Ability of this HCA to support multiple page sizes per Memory Region. */
2270      pseudo_bit_t	bl[0x00001];           /* Ability of this HCA to support Block List Physical Buffer Lists. (The device does not supports Block List) */
2271      pseudo_bit_t	zb[0x00001];           /* Zero Based region/windows supported */
2272      pseudo_bit_t	lif[0x00001];          /* Ability of this HCA to support Local Invalidate Fencing. */
2273      pseudo_bit_t	reserved38[0x00002];
2274      pseudo_bit_t	log_pbl_sz[0x00006];   /* Log2 of the Maximum Physical Buffer List size in Bytes supported by this HCA when invoking the Allocate L_Key verb.
2275                                                    */
2276      pseudo_bit_t	reserved39[0x00012];
2277  /* -------------- */
2278      pseudo_bit_t	resd_lkey[0x00020];    /* The value of the reserved Lkey for Base Memory Management Extension */
2279  /* -------------- */
2280      pseudo_bit_t	lamr[0x00001];         /* When set the device requires local attached memory in order to operate.
2281                                                   When set,  ICM pages, Firmware Area and ICM auxiliary pages must be allocated in the local attached memory. */
2282      pseudo_bit_t	reserved40[0x0001f];
2283  /* -------------- */
2284      pseudo_bit_t	max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */
2285  /* -------------- */
2286      pseudo_bit_t	max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */
2287  /* -------------- */
2288      pseudo_bit_t	reserved41[0x002c0];
2289  /* -------------- */
2290  };
2291  
2292  /* QUERY_ADAPTER Parameters Block */
2293  
2294  struct arbelprm_query_adapter_st {	/* Little Endian */
2295      pseudo_bit_t	reserved0[0x00080];
2296  /* -------------- */
2297      pseudo_bit_t	reserved1[0x00018];
2298      pseudo_bit_t	intapin[0x00008];      /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */
2299  /* -------------- */
2300      pseudo_bit_t	reserved2[0x00060];
2301  /* -------------- */
2302      struct arbelprm_vsd_st	vsd;
2303  /* -------------- */
2304  };
2305  
2306  /* QUERY_FW Parameters Block */
2307  
2308  struct arbelprm_query_fw_st {	/* Little Endian */
2309      pseudo_bit_t	fw_rev_major[0x00010]; /* Firmware Revision - Major */
2310      pseudo_bit_t	fw_pages[0x00010];     /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
2311  /* -------------- */
2312      pseudo_bit_t	fw_rev_minor[0x00010]; /* Firmware Revision - Minor */
2313      pseudo_bit_t	fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
2314  /* -------------- */
2315      pseudo_bit_t	cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
2316      pseudo_bit_t	reserved0[0x0000e];
2317      pseudo_bit_t	wqe_h_mode[0x00001];   /* Hermon mode. If '1', then WQE and AV format is the advanced format */
2318      pseudo_bit_t	zb_wq_cq[0x00001];     /* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */
2319  /* -------------- */
2320      pseudo_bit_t	log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
2321      pseudo_bit_t	reserved1[0x00017];
2322      pseudo_bit_t	dt[0x00001];           /* Debug Trace Support
2323                                                   0 - Debug trace is not supported
2324                                                   1 - Debug trace is supported */
2325  /* -------------- */
2326      pseudo_bit_t	cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */
2327      pseudo_bit_t	reserved2[0x0001f];
2328  /* -------------- */
2329      pseudo_bit_t	reserved3[0x00060];
2330  /* -------------- */
2331      pseudo_bit_t	clr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address.
2332                                                   Points to 64 bit register. */
2333  /* -------------- */
2334      pseudo_bit_t	clr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address.
2335                                                   Points to 64 bit register. */
2336  /* -------------- */
2337      pseudo_bit_t	reserved4[0x00040];
2338  /* -------------- */
2339      pseudo_bit_t	error_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
2340  /* -------------- */
2341      pseudo_bit_t	error_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
2342  /* -------------- */
2343      pseudo_bit_t	error_buf_size[0x00020];/* Size in words */
2344  /* -------------- */
2345      pseudo_bit_t	reserved5[0x00020];
2346  /* -------------- */
2347      pseudo_bit_t	eq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address.
2348                                                   Points to 64 bit register.
2349                                                   Setting bit x in the offset, arms EQ number x.
2350                                                    */
2351  /* -------------- */
2352      pseudo_bit_t	eq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address.
2353                                                   Points to 64 bit register.
2354                                                   Setting bit x in the offset, arms EQ number x. */
2355  /* -------------- */
2356      pseudo_bit_t	eq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address.
2357                                                   Points to a the EQ Set CI DBs Table base address. */
2358  /* -------------- */
2359      pseudo_bit_t	eq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address.
2360                                                   Points to a the EQ Set CI DBs Table base address. */
2361  /* -------------- */
2362      pseudo_bit_t	cmd_db_dw1[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2363      pseudo_bit_t	cmd_db_dw0[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2364  /* -------------- */
2365      pseudo_bit_t	cmd_db_dw3[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2366      pseudo_bit_t	cmd_db_dw2[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2367  /* -------------- */
2368      pseudo_bit_t	cmd_db_dw5[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2369      pseudo_bit_t	cmd_db_dw4[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2370  /* -------------- */
2371      pseudo_bit_t	cmd_db_dw7[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2372      pseudo_bit_t	cmd_db_dw6[0x00010];   /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2373  /* -------------- */
2374      pseudo_bit_t	cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
2375  /* -------------- */
2376      pseudo_bit_t	cmd_db_addr_base_l[0x00020];/* Low  bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
2377  /* -------------- */
2378      pseudo_bit_t	reserved6[0x004c0];
2379  /* -------------- */
2380  };
2381  
2382  /* ACCESS_LAM */
2383  
2384  struct arbelprm_access_lam_st {	/* Little Endian */
2385      struct arbelprm_access_lam_inject_errors_st	access_lam_inject_errors;
2386  /* -------------- */
2387      pseudo_bit_t	reserved0[0x00080];
2388  /* -------------- */
2389  };
2390  
2391  /* ENABLE_LAM Parameters Block */
2392  
2393  struct arbelprm_enable_lam_st {	/* Little Endian */
2394      pseudo_bit_t	lam_start_adr_h[0x00020];/* LAM start address [63:32] */
2395  /* -------------- */
2396      pseudo_bit_t	lam_start_adr_l[0x00020];/* LAM start address [31:0] */
2397  /* -------------- */
2398      pseudo_bit_t	lam_end_adr_h[0x00020];/* LAM end address [63:32] */
2399  /* -------------- */
2400      pseudo_bit_t	lam_end_adr_l[0x00020];/* LAM end address [31:0] */
2401  /* -------------- */
2402      pseudo_bit_t	di[0x00002];           /* Data Integrity Configuration:
2403                                                   00 - none
2404                                                   01 - Parity
2405                                                   10 - ECC Detection Only
2406                                                   11 - ECC With Correction */
2407      pseudo_bit_t	ap[0x00002];           /* Auto Precharge Mode
2408                                                   00 - No auto precharge
2409                                                   01 - Auto precharge per transaction
2410                                                   10 - Auto precharge per 64 bytes
2411                                                   11 - reserved */
2412      pseudo_bit_t	dh[0x00001];           /* When set, LAM is Hidden and can not be accessed directly from the PCI bus. */
2413      pseudo_bit_t	reserved0[0x0001b];
2414  /* -------------- */
2415      pseudo_bit_t	reserved1[0x00160];
2416  /* -------------- */
2417      struct arbelprm_dimminfo_st	dimm0;  /* Logical DIMM 0 Parameters */
2418  /* -------------- */
2419      struct arbelprm_dimminfo_st	dimm1;  /* Logical DIMM 1 Parameters */
2420  /* -------------- */
2421      pseudo_bit_t	reserved2[0x00400];
2422  /* -------------- */
2423  };
2424  
2425  /* Memory Access Parameters for UD Address Vector Table */
2426  
2427  struct arbelprm_udavtable_memory_parameters_st {	/* Little Endian */
2428      pseudo_bit_t	l_key[0x00020];        /* L_Key used to access TPT */
2429  /* -------------- */
2430      pseudo_bit_t	pd[0x00018];           /* PD used by TPT for matching against PD of region entry being accessed. */
2431      pseudo_bit_t	reserved0[0x00005];
2432      pseudo_bit_t	xlation_en[0x00001];   /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
2433      pseudo_bit_t	reserved1[0x00002];
2434  /* -------------- */
2435  };
2436  
2437  /* INIT_HCA & QUERY_HCA Parameters Block */
2438  
2439  struct arbelprm_init_hca_st {	/* Little Endian */
2440      pseudo_bit_t	reserved0[0x00060];
2441  /* -------------- */
2442      pseudo_bit_t	reserved1[0x00010];
2443      pseudo_bit_t	time_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented.
2444                                                   The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond)
2445                                                   When sets to Zero, timestamp reporting in the CQE is disabled.
2446                                                   This feature is currently not supported.
2447                                                    */
2448      pseudo_bit_t	hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */
2449  /* -------------- */
2450      pseudo_bit_t	reserved2[0x00008];
2451      pseudo_bit_t	router_qp[0x00010];    /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.
2452                                                   Valid only if RE bit is set */
2453      pseudo_bit_t	reserved3[0x00007];
2454      pseudo_bit_t	re[0x00001];           /* Router Mode Enable
2455                                                   If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */
2456  /* -------------- */
2457      pseudo_bit_t	udp[0x00001];          /* UD Port Check Enable
2458                                                   0 - Port field in Address Vector is ignored
2459                                                   1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
2460      pseudo_bit_t	he[0x00001];           /* Host Endianess - Used for Atomic Operations
2461                                                   0 - Host is Little Endian
2462                                                   1 - Host is Big endian
2463                                                    */
2464      pseudo_bit_t	reserved4[0x00001];
2465      pseudo_bit_t	ce[0x00001];           /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
2466      pseudo_bit_t	sph[0x00001];          /* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet
2467                                                   1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet
2468                                                    */
2469      pseudo_bit_t	rph[0x00001];          /* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet
2470                                                   1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet
2471                                                    */
2472      pseudo_bit_t	reserved5[0x00002];
2473      pseudo_bit_t	responder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester .
2474                                                   responder_exu/16 = (number of responder exu engines)/(total number of engines)
2475                                                   Legal values are 0x0-0xF. 0 is "auto".
2476  
2477                                                    */
2478      pseudo_bit_t	reserved6[0x00004];
2479      pseudo_bit_t	wqe_quota[0x0000f];    /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */
2480      pseudo_bit_t	wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */
2481  /* -------------- */
2482      pseudo_bit_t	reserved7[0x00040];
2483  /* -------------- */
2484      struct arbelprm_qpcbaseaddr_st	qpc_eec_cqc_eqc_rdb_parameters;
2485  /* -------------- */
2486      pseudo_bit_t	reserved8[0x00100];
2487  /* -------------- */
2488      struct arbelprm_multicastparam_st	multicast_parameters;
2489  /* -------------- */
2490      pseudo_bit_t	reserved9[0x00080];
2491  /* -------------- */
2492      struct arbelprm_tptparams_st	tpt_parameters;
2493  /* -------------- */
2494      pseudo_bit_t	reserved10[0x00080];
2495  /* -------------- */
2496      struct arbelprm_uar_params_st	uar_parameters;/* UAR Parameters */
2497  /* -------------- */
2498      pseudo_bit_t	reserved11[0x00600];
2499  /* -------------- */
2500  };
2501  
2502  /* Event Queue Context Table Entry */
2503  
2504  struct arbelprm_eqc_st {	/* Little Endian */
2505      pseudo_bit_t	reserved0[0x00008];
2506      pseudo_bit_t	st[0x00004];           /* Event delivery state machine
2507                                                   0x9 - Armed
2508                                                   0xA - Fired
2509                                                   0xB - Always_Armed (auto-rearm)
2510                                                   other - reserved */
2511      pseudo_bit_t	reserved1[0x00005];
2512      pseudo_bit_t	oi[0x00001];           /* Oerrun ignore.
2513                                                   If set, HW will not check EQ full condition when writing new EQEs. */
2514      pseudo_bit_t	tr[0x00001];           /* Translation Required. If set - EQ access undergo address translation. */
2515      pseudo_bit_t	reserved2[0x00005];
2516      pseudo_bit_t	owner[0x00004];        /* 0 - SW ownership
2517                                                   1 - HW ownership
2518                                                   Valid for the QUERY_EQ and HW2SW_EQ commands only */
2519      pseudo_bit_t	status[0x00004];       /* EQ status:
2520                                                   0000 - OK
2521                                                   1010 - EQ write failure
2522                                                   Valid for the QUERY_EQ and HW2SW_EQ commands only */
2523  /* -------------- */
2524      pseudo_bit_t	start_address_h[0x00020];/* Start Address of Event Queue[63:32]. */
2525  /* -------------- */
2526      pseudo_bit_t	start_address_l[0x00020];/* Start Address of Event Queue[31:0].
2527                                                   Must be aligned on 32-byte boundary */
2528  /* -------------- */
2529      pseudo_bit_t	reserved3[0x00018];
2530      pseudo_bit_t	log_eq_size[0x00005];  /* Amount of entries in this EQ is 2^log_eq_size.
2531                                                   Log_eq_size must be bigger than 1.
2532                                                   Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */
2533      pseudo_bit_t	reserved4[0x00003];
2534  /* -------------- */
2535      pseudo_bit_t	reserved5[0x00020];
2536  /* -------------- */
2537      pseudo_bit_t	intr[0x00008];         /* Interrupt (message) to be generated to report event to INT layer.
2538                                                   00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express.
2539                                                   10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported).
2540                                                   All other values are reserved and should not be used.
2541  
2542                                                   If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */
2543      pseudo_bit_t	reserved6[0x00018];
2544  /* -------------- */
2545      pseudo_bit_t	pd[0x00018];           /* PD to be used to access EQ */
2546      pseudo_bit_t	reserved7[0x00008];
2547  /* -------------- */
2548      pseudo_bit_t	lkey[0x00020];         /* Memory key (L-Key) to be used to access EQ */
2549  /* -------------- */
2550      pseudo_bit_t	reserved8[0x00040];
2551  /* -------------- */
2552      pseudo_bit_t	consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue.
2553                                                   Must be initalized to zero while opening EQ */
2554  /* -------------- */
2555      pseudo_bit_t	producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA.
2556                                                   Must be initalized to zero while opening EQ. */
2557  /* -------------- */
2558      pseudo_bit_t	reserved9[0x00080];
2559  /* -------------- */
2560  };
2561  
2562  /* Memory Translation Table (MTT) Entry */
2563  
2564  struct arbelprm_mtt_st {	/* Little Endian */
2565      pseudo_bit_t	ptag_h[0x00020];       /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2566  /* -------------- */
2567      pseudo_bit_t	p[0x00001];            /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
2568      pseudo_bit_t	reserved0[0x0000b];
2569      pseudo_bit_t	ptag_l[0x00014];       /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2570  /* -------------- */
2571  };
2572  
2573  /* Memory Protection Table (MPT) Entry */
2574  
2575  struct arbelprm_mpt_st {	/* Little Endian */
2576      pseudo_bit_t	reserved0[0x00008];
2577      pseudo_bit_t	r_w[0x00001];          /* Defines whether this entry is Region (1) or Window (0) */
2578      pseudo_bit_t	pa[0x00001];           /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */
2579      pseudo_bit_t	lr[0x00001];           /* If set - local read access enabled */
2580      pseudo_bit_t	lw[0x00001];           /* If set - local write access enabled */
2581      pseudo_bit_t	rr[0x00001];           /* If set - remote read access enabled. */
2582      pseudo_bit_t	rw[0x00001];           /* If set - remote write access enabled */
2583      pseudo_bit_t	a[0x00001];            /* If set - remote Atomic access is enabled */
2584      pseudo_bit_t	eb[0x00001];           /* If set - Bind is enabled. Valid for region entry only. */
2585      pseudo_bit_t	reserved1[0x0000c];
2586      pseudo_bit_t	status[0x00004];       /* Region/Window Status
2587                                                   0xF - not valid (SW ownership)
2588                                                   0x3 - FREE state
2589                                                   else - HW ownership
2590                                                   Unbound Type I windows are doneted reg_wnd_len field equals zero.
2591                                                   Unbound Type II windows are donated by Status=FREE. */
2592  /* -------------- */
2593      pseudo_bit_t	page_size[0x00005];    /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
2594                                                   page_size should be less than 20. */
2595      pseudo_bit_t	reserved2[0x00002];
2596      pseudo_bit_t	type[0x00001];         /* Applicable for windows only, must be zero for regions
2597                                                   0 - Type one window
2598                                                   1 - Type two window */
2599      pseudo_bit_t	qpn[0x00018];          /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */
2600  /* -------------- */
2601      pseudo_bit_t	mem_key[0x00020];      /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}.
2602                                                    */
2603  /* -------------- */
2604      pseudo_bit_t	pd[0x00018];           /* Protection Domain */
2605      pseudo_bit_t	reserved3[0x00001];
2606      pseudo_bit_t	ei[0x00001];           /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region.
2607                                                   Must be set for type2 windows and non-shared physical memory regions.
2608                                                   Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */
2609      pseudo_bit_t	zb[0x00001];           /* When set, this region is Zero Based Region */
2610      pseudo_bit_t	fre[0x00001];          /* When set, Fast Registration Operations can be executed on this region */
2611      pseudo_bit_t	rae[0x00001];          /* When set, remote access can be enabled on this region.
2612                                                   Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT.
2613                                                   If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail.
2614                                                    */
2615      pseudo_bit_t	reserved4[0x00003];
2616  /* -------------- */
2617      pseudo_bit_t	start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */
2618  /* -------------- */
2619      pseudo_bit_t	start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */
2620  /* -------------- */
2621      pseudo_bit_t	reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */
2622  /* -------------- */
2623      pseudo_bit_t	reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */
2624  /* -------------- */
2625      pseudo_bit_t	lkey[0x00020];         /* Must be 0 for SW2HW_MPT.
2626                                                   On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.
2627                                                   The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
2628  /* -------------- */
2629      pseudo_bit_t	win_cnt[0x00020];      /* Number of windows bound to this region. Valid for regions only.
2630                                                   The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
2631  /* -------------- */
2632      pseudo_bit_t	reserved5[0x00020];
2633  /* -------------- */
2634      pseudo_bit_t	mtt_adr_h[0x00006];    /* Base (first) address of the MTT relative to MTT base in the ICM */
2635      pseudo_bit_t	reserved6[0x0001a];
2636  /* -------------- */
2637      pseudo_bit_t	reserved7[0x00003];
2638      pseudo_bit_t	mtt_adr_l[0x0001d];    /* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */
2639  /* -------------- */
2640      pseudo_bit_t	mtt_sz[0x00020];       /* Number of MTT entries allocated for this MR.
2641                                                   When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved.
2642                                                   When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value  is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */
2643  /* -------------- */
2644      pseudo_bit_t	reserved8[0x00040];
2645  /* -------------- */
2646  };
2647  
2648  /* Completion Queue Context Table Entry */
2649  
2650  struct arbelprm_completion_queue_context_st {	/* Little Endian */
2651      pseudo_bit_t	reserved0[0x00008];
2652      pseudo_bit_t	st[0x00004];           /* Event delivery state machine
2653                                                   0x0 - reserved
2654                                                   0x9 - ARMED (Request for Notification)
2655                                                   0x6 - ARMED SOLICITED (Request Solicited Notification)
2656                                                   0xA - FIRED
2657                                                   other - reserved
2658  
2659                                                   Must be 0x0 in CQ initialization.
2660                                                   Valid for the QUERY_CQ and HW2SW_CQ commands only. */
2661      pseudo_bit_t	reserved1[0x00005];
2662      pseudo_bit_t	oi[0x00001];           /* When set, overrun ignore is enabled.
2663                                                   When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */
2664      pseudo_bit_t	reserved2[0x0000a];
2665      pseudo_bit_t	status[0x00004];       /* CQ status
2666                                                   0000 - OK
2667                                                   1001 - CQ overflow
2668                                                   1010 - CQ write failure
2669                                                   Valid for the QUERY_CQ and HW2SW_CQ commands only */
2670  /* -------------- */
2671      pseudo_bit_t	start_address_h[0x00020];/* Start address of CQ[63:32].
2672                                                   Must be aligned on CQE size (32 bytes) */
2673  /* -------------- */
2674      pseudo_bit_t	start_address_l[0x00020];/* Start address of CQ[31:0].
2675                                                   Must be aligned on CQE size (32 bytes) */
2676  /* -------------- */
2677      pseudo_bit_t	usr_page[0x00018];     /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
2678      pseudo_bit_t	log_cq_size[0x00005];  /* Log (base 2) of the CQ size (in entries).
2679                                                   Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */
2680      pseudo_bit_t	reserved3[0x00003];
2681  /* -------------- */
2682      pseudo_bit_t	reserved4[0x00020];
2683  /* -------------- */
2684      pseudo_bit_t	c_eqn[0x00008];        /* Event Queue this CQ reports completion events to.
2685                                                   Valid values are 0 to 63
2686                                                   If configured to value other than 0-63, completion events will not be reported on the CQ. */
2687      pseudo_bit_t	reserved5[0x00018];
2688  /* -------------- */
2689      pseudo_bit_t	pd[0x00018];           /* Protection Domain to be used to access CQ.
2690                                                   Must be the same PD of the CQ L_Key. */
2691      pseudo_bit_t	reserved6[0x00008];
2692  /* -------------- */
2693      pseudo_bit_t	l_key[0x00020];        /* Memory key (L_Key) to be used to access CQ */
2694  /* -------------- */
2695      pseudo_bit_t	last_notified_indx[0x00020];/* Maintained by HW.
2696                                                   Valid for QUERY_CQ and HW2SW_CQ commands only. */
2697  /* -------------- */
2698      pseudo_bit_t	solicit_producer_indx[0x00020];/* Maintained by HW.
2699                                                   Valid for QUERY_CQ and HW2SW_CQ commands only.
2700                                                    */
2701  /* -------------- */
2702      pseudo_bit_t	consumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ.
2703                                                   Must be 0x0 in CQ initialization.
2704                                                   Valid for the QUERY_CQ and HW2SW_CQ commands only. */
2705  /* -------------- */
2706      pseudo_bit_t	producer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ.
2707                                                   CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added..
2708                                                   Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
2709  /* -------------- */
2710      pseudo_bit_t	cqn[0x00018];          /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table
2711                                                   Valid for the QUERY_CQ and HW2SW_CQ commands only */
2712      pseudo_bit_t	reserved7[0x00008];
2713  /* -------------- */
2714      pseudo_bit_t	cq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry.
2715                                                   HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record.
2716                                                   This value can be retrieved from the HW in the QUERY_CQ command. */
2717  /* -------------- */
2718      pseudo_bit_t	cq_state_db_record[0x00020];/* Index in the UAR Context Table Entry.
2719                                                   HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record.
2720                                                   This value can be retrieved from the HW in the QUERY_CQ command. */
2721  /* -------------- */
2722      pseudo_bit_t	reserved8[0x00020];
2723  /* -------------- */
2724  };
2725  
2726  /* GPIO_event_data */
2727  
2728  struct arbelprm_gpio_event_data_st {	/* Little Endian */
2729      pseudo_bit_t	reserved0[0x00060];
2730  /* -------------- */
2731      pseudo_bit_t	gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2732  /* -------------- */
2733      pseudo_bit_t	gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2734  /* -------------- */
2735      pseudo_bit_t	reserved1[0x00020];
2736  /* -------------- */
2737  };
2738  
2739  /* Event_data Field - QP/EE Events */
2740  
2741  struct arbelprm_qp_ee_event_st {	/* Little Endian */
2742      pseudo_bit_t	qpn_een[0x00018];      /* QP/EE/SRQ number event is reported for */
2743      pseudo_bit_t	reserved0[0x00008];
2744  /* -------------- */
2745      pseudo_bit_t	reserved1[0x00020];
2746  /* -------------- */
2747      pseudo_bit_t	reserved2[0x0001c];
2748      pseudo_bit_t	e_q[0x00001];          /* If set - EEN if cleared - QP in the QPN/EEN field
2749                                                   Not valid on SRQ events */
2750      pseudo_bit_t	reserved3[0x00003];
2751  /* -------------- */
2752      pseudo_bit_t	reserved4[0x00060];
2753  /* -------------- */
2754  };
2755  
2756  /* InfiniHost-III-EX Type0 Configuration Header */
2757  
2758  struct arbelprm_mt25208_type0_st {	/* Little Endian */
2759      pseudo_bit_t	vendor_id[0x00010];    /* Hardwired to 0x15B3 */
2760      pseudo_bit_t	device_id[0x00010];    /* 25208 (decimal) - InfiniHost-III compatible mode
2761                                                   25218 (decimal) - InfiniHost-III EX mode (the mode described in this manual)
2762                                                   25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode
2763                                                    */
2764  /* -------------- */
2765      pseudo_bit_t	command[0x00010];      /* PCI Command Register */
2766      pseudo_bit_t	status[0x00010];       /* PCI Status Register */
2767  /* -------------- */
2768      pseudo_bit_t	revision_id[0x00008];
2769      pseudo_bit_t	class_code_hca_class_code[0x00018];
2770  /* -------------- */
2771      pseudo_bit_t	cache_line_size[0x00008];/* Cache Line Size */
2772      pseudo_bit_t	latency_timer[0x00008];
2773      pseudo_bit_t	header_type[0x00008];  /* hardwired to zero */
2774      pseudo_bit_t	bist[0x00008];
2775  /* -------------- */
2776      pseudo_bit_t	bar0_ctrl[0x00004];    /* hard-wired to 0100 */
2777      pseudo_bit_t	reserved0[0x00010];
2778      pseudo_bit_t	bar0_l[0x0000c];       /* Lower bits of BAR0 (Device Configuration Space) */
2779  /* -------------- */
2780      pseudo_bit_t	bar0_h[0x00020];       /* Upper 32 bits of BAR0 (Device Configuration Space) */
2781  /* -------------- */
2782      pseudo_bit_t	bar1_ctrl[0x00004];    /* Hardwired to 1100 */
2783      pseudo_bit_t	reserved1[0x00010];
2784      pseudo_bit_t	bar1_l[0x0000c];       /* Lower bits of BAR1 (User Access Region - UAR - space) */
2785  /* -------------- */
2786      pseudo_bit_t	bar1_h[0x00020];       /* upper 32 bits of BAR1 (User Access Region - UAR - space) */
2787  /* -------------- */
2788      pseudo_bit_t	bar2_ctrl[0x00004];    /* Hardwired to 1100 */
2789      pseudo_bit_t	reserved2[0x00010];
2790      pseudo_bit_t	bar2_l[0x0000c];       /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2791  /* -------------- */
2792      pseudo_bit_t	bar2_h[0x00020];       /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2793  /* -------------- */
2794      pseudo_bit_t	cardbus_cis_pointer[0x00020];
2795  /* -------------- */
2796      pseudo_bit_t	subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
2797      pseudo_bit_t	subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */
2798  /* -------------- */
2799      pseudo_bit_t	expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2800      pseudo_bit_t	reserved3[0x0000a];
2801      pseudo_bit_t	expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2802  /* -------------- */
2803      pseudo_bit_t	capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
2804      pseudo_bit_t	reserved4[0x00018];
2805  /* -------------- */
2806      pseudo_bit_t	reserved5[0x00020];
2807  /* -------------- */
2808      pseudo_bit_t	interrupt_line[0x00008];
2809      pseudo_bit_t	interrupt_pin[0x00008];
2810      pseudo_bit_t	min_gnt[0x00008];
2811      pseudo_bit_t	max_latency[0x00008];
2812  /* -------------- */
2813      pseudo_bit_t	reserved6[0x00100];
2814  /* -------------- */
2815      pseudo_bit_t	msi_cap_id[0x00008];
2816      pseudo_bit_t	msi_next_cap_ptr[0x00008];
2817      pseudo_bit_t	msi_en[0x00001];
2818      pseudo_bit_t	multiple_msg_cap[0x00003];
2819      pseudo_bit_t	multiple_msg_en[0x00003];
2820      pseudo_bit_t	cap_64_bit_addr[0x00001];
2821      pseudo_bit_t	reserved7[0x00008];
2822  /* -------------- */
2823      pseudo_bit_t	msg_addr_l[0x00020];
2824  /* -------------- */
2825      pseudo_bit_t	msg_addr_h[0x00020];
2826  /* -------------- */
2827      pseudo_bit_t	msg_data[0x00010];
2828      pseudo_bit_t	reserved8[0x00010];
2829  /* -------------- */
2830      pseudo_bit_t	reserved9[0x00080];
2831  /* -------------- */
2832      pseudo_bit_t	pm_cap_id[0x00008];    /* Power management capability ID - 01h */
2833      pseudo_bit_t	pm_next_cap_ptr[0x00008];
2834      pseudo_bit_t	pm_cap[0x00010];       /* [2:0] Version - 02h
2835                                                   [3] PME clock - 0h
2836                                                   [4] RsvP
2837                                                   [5] Device specific initialization - 0h
2838                                                   [8:6] AUX current - 0h
2839                                                   [9] D1 support - 0h
2840                                                   [10] D2 support - 0h
2841                                                   [15:11] PME support - 0h */
2842  /* -------------- */
2843      pseudo_bit_t	pm_status_control[0x00010];/* [14:13] - Data scale - 0h */
2844      pseudo_bit_t	pm_control_status_brdg_ext[0x00008];
2845      pseudo_bit_t	data[0x00008];
2846  /* -------------- */
2847      pseudo_bit_t	reserved10[0x00040];
2848  /* -------------- */
2849      pseudo_bit_t	vpd_cap_id[0x00008];   /* 03h */
2850      pseudo_bit_t	vpd_next_cap_id[0x00008];
2851      pseudo_bit_t	vpd_address[0x0000f];
2852      pseudo_bit_t	f[0x00001];
2853  /* -------------- */
2854      pseudo_bit_t	vpd_data[0x00020];
2855  /* -------------- */
2856      pseudo_bit_t	reserved11[0x00040];
2857  /* -------------- */
2858      pseudo_bit_t	pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */
2859      pseudo_bit_t	pciex_next_cap_ptr[0x00008];
2860      pseudo_bit_t	pciex_cap[0x00010];    /* [3:0] Capability version - 1h
2861                                                   [7:4] Device/Port Type - 0h
2862                                                   [8] Slot implemented - 0h
2863                                                   [13:9] Interrupt message number
2864                                                    */
2865  /* -------------- */
2866      pseudo_bit_t	device_cap[0x00020];   /* [2:0] Max_Payload_Size supported - 2h
2867                                                   [4:3] Phantom Function supported - 0h
2868                                                   [5] Extended Tag Filed supported - 0h
2869                                                   [8:6] Endpoint L0s Acceptable Latency - TBD
2870                                                   [11:9] Endpoint L1 Acceptable Latency - TBD
2871                                                   [12] Attention Button Present - configured through InfiniBurn
2872                                                   [13] Attention Indicator Present - configured through InfiniBurn
2873                                                   [14] Power Indicator Present - configured through InfiniBurn
2874                                                   [25:18] Captured Slot Power Limit Value
2875                                                   [27:26] Captured Slot Power Limit Scale */
2876  /* -------------- */
2877      pseudo_bit_t	device_control[0x00010];
2878      pseudo_bit_t	device_status[0x00010];
2879  /* -------------- */
2880      pseudo_bit_t	link_cap[0x00020];     /* [3:0] Maximum Link Speed - 1h
2881                                                   [9:4] Maximum Link Width - 8h
2882                                                   [11:10] Active State Power Management Support - 3h
2883                                                   [14:12] L0s Exit Latency - TBD
2884                                                   [17:15] L1 Exit Latency - TBD
2885                                                   [31:24] Port Number - 0h */
2886  /* -------------- */
2887      pseudo_bit_t	link_control[0x00010];
2888      pseudo_bit_t	link_status[0x00010];  /* [3:0] Link Speed - 1h
2889                                                   [9:4] Negotiated Link Width
2890                                                   [12] Slot clock configuration - 1h */
2891  /* -------------- */
2892      pseudo_bit_t	reserved12[0x00260];
2893  /* -------------- */
2894      pseudo_bit_t	advanced_error_reporting_cap_id[0x00010];/* 0001h. */
2895      pseudo_bit_t	capability_version[0x00004];/* 1h */
2896      pseudo_bit_t	next_capability_offset[0x0000c];/* 0h */
2897  /* -------------- */
2898      pseudo_bit_t	uncorrectable_error_status_register[0x00020];/* 0 Training Error Status
2899                                                   4 Data Link Protocol Error Status
2900                                                   12 Poisoned TLP Status
2901                                                   13 Flow Control Protocol Error Status
2902                                                   14 Completion Timeout Status
2903                                                   15 Completer Abort Status
2904                                                   16 Unexpected Completion Status
2905                                                   17 Receiver Overflow Status
2906                                                   18 Malformed TLP Status
2907                                                   19 ECRC Error Status
2908                                                   20 Unsupported Request Error Status */
2909  /* -------------- */
2910      pseudo_bit_t	uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask
2911                                                   4 Data Link Protocol Error Mask
2912                                                   12 Poisoned TLP Mask
2913                                                   13 Flow Control Protocol Error Mask
2914                                                   14 Completion Timeout Mask
2915                                                   15 Completer Abort Mask
2916                                                   16 Unexpected Completion Mask
2917                                                   17 Receiver Overflow Mask
2918                                                   18 Malformed TLP Mask
2919                                                   19 ECRC Error Mask
2920                                                   20 Unsupported Request Error Mask */
2921  /* -------------- */
2922      pseudo_bit_t	uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity
2923                                                   4 Data Link Protocol Error Severity
2924                                                   12 Poisoned TLP Severity
2925                                                   13 Flow Control Protocol Error Severity
2926                                                   14 Completion Timeout Severity
2927                                                   15 Completer Abort Severity
2928                                                   16 Unexpected Completion Severity
2929                                                   17 Receiver Overflow Severity
2930                                                   18 Malformed TLP Severity
2931                                                   19 ECRC Error Severity
2932                                                   20 Unsupported Request Error Severity */
2933  /* -------------- */
2934      pseudo_bit_t	correctable_error_status_register[0x00020];/* 0 Receiver Error Status
2935                                                   6 Bad TLP Status
2936                                                   7 Bad DLLP Status
2937                                                   8 REPLAY_NUM Rollover Status
2938                                                   12 Replay Timer Timeout Status */
2939  /* -------------- */
2940      pseudo_bit_t	correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask
2941                                                   6 Bad TLP Mask
2942                                                   7 Bad DLLP Mask
2943                                                   8 REPLAY_NUM Rollover Mask
2944                                                   12 Replay Timer Timeout Mask */
2945  /* -------------- */
2946      pseudo_bit_t	advance_error_capabilities_and_control_register[0x00020];
2947  /* -------------- */
2948      struct arbelprm_header_log_register_st	header_log_register;
2949  /* -------------- */
2950      pseudo_bit_t	reserved13[0x006a0];
2951  /* -------------- */
2952  };
2953  
2954  /* Event Data Field - Performance Monitor */
2955  
2956  struct arbelprm_performance_monitor_event_st {	/* Little Endian */
2957      struct arbelprm_performance_monitors_st	performance_monitor_snapshot;/* Performance monitor snapshot */
2958  /* -------------- */
2959      pseudo_bit_t	monitor_number[0x00008];/* 0x01 - SQPC
2960                                                   0x02 - RQPC
2961                                                   0x03 - CQC
2962                                                   0x04 - Rkey
2963                                                   0x05 - TLB
2964                                                   0x06 - port0
2965                                                   0x07 - port1 */
2966      pseudo_bit_t	reserved0[0x00018];
2967  /* -------------- */
2968      pseudo_bit_t	reserved1[0x00040];
2969  /* -------------- */
2970  };
2971  
2972  /* Event_data Field - Page Faults */
2973  
2974  struct arbelprm_page_fault_event_data_st {	/* Little Endian */
2975      pseudo_bit_t	va_h[0x00020];         /* Virtual Address[63:32] this page fault is reported on */
2976  /* -------------- */
2977      pseudo_bit_t	va_l[0x00020];         /* Virtual Address[63:32] this page fault is reported on */
2978  /* -------------- */
2979      pseudo_bit_t	mem_key[0x00020];      /* Memory Key this page fault is reported on */
2980  /* -------------- */
2981      pseudo_bit_t	qp[0x00018];           /* QP this page fault is reported on */
2982      pseudo_bit_t	reserved0[0x00003];
2983      pseudo_bit_t	a[0x00001];            /* If set the memory access that caused the page fault was atomic */
2984      pseudo_bit_t	lw[0x00001];           /* If set the memory access that caused the page fault was local write */
2985      pseudo_bit_t	lr[0x00001];           /* If set the memory access that caused the page fault was local read */
2986      pseudo_bit_t	rw[0x00001];           /* If set the memory access that caused the page fault was remote write */
2987      pseudo_bit_t	rr[0x00001];           /* If set the memory access that caused the page fault was remote read */
2988  /* -------------- */
2989      pseudo_bit_t	pd[0x00018];           /* PD this page fault is reported on */
2990      pseudo_bit_t	reserved1[0x00008];
2991  /* -------------- */
2992      pseudo_bit_t	prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
2993  /* -------------- */
2994  };
2995  
2996  /* WQE segments format */
2997  
2998  struct arbelprm_wqe_segment_st {	/* Little Endian */
2999      struct arbelprm_send_wqe_segment_st	send_wqe_segment;/* Send WQE segment format */
3000  /* -------------- */
3001      pseudo_bit_t	reserved0[0x00280];
3002  /* -------------- */
3003      struct arbelprm_wqe_segment_ctrl_mlx_st	mlx_wqe_segment_ctrl;/* MLX WQE segment format */
3004  /* -------------- */
3005      pseudo_bit_t	reserved1[0x00100];
3006  /* -------------- */
3007      struct arbelprm_wqe_segment_ctrl_recv_st	recv_wqe_segment_ctrl;/* Receive segment format */
3008  /* -------------- */
3009      pseudo_bit_t	reserved2[0x00080];
3010  /* -------------- */
3011  };
3012  
3013  /* Event_data Field - Port State Change */
3014  
3015  struct arbelprm_port_state_change_st {	/* Little Endian */
3016      pseudo_bit_t	reserved0[0x00040];
3017  /* -------------- */
3018      pseudo_bit_t	reserved1[0x0001c];
3019      pseudo_bit_t	p[0x00002];            /* Port number (1 or 2) */
3020      pseudo_bit_t	reserved2[0x00002];
3021  /* -------------- */
3022      pseudo_bit_t	reserved3[0x00060];
3023  /* -------------- */
3024  };
3025  
3026  /* Event_data Field - Completion Queue Error */
3027  
3028  struct arbelprm_completion_queue_error_st {	/* Little Endian */
3029      pseudo_bit_t	cqn[0x00018];          /* CQ number event is reported for */
3030      pseudo_bit_t	reserved0[0x00008];
3031  /* -------------- */
3032      pseudo_bit_t	reserved1[0x00020];
3033  /* -------------- */
3034      pseudo_bit_t	syndrome[0x00008];     /* Error syndrome
3035                                                   0x01 - CQ overrun
3036                                                   0x02 - CQ access violation error */
3037      pseudo_bit_t	reserved2[0x00018];
3038  /* -------------- */
3039      pseudo_bit_t	reserved3[0x00060];
3040  /* -------------- */
3041  };
3042  
3043  /* Event_data Field - Completion Event */
3044  
3045  struct arbelprm_completion_event_st {	/* Little Endian */
3046      pseudo_bit_t	cqn[0x00018];          /* CQ number event is reported for */
3047      pseudo_bit_t	reserved0[0x00008];
3048  /* -------------- */
3049      pseudo_bit_t	reserved1[0x000a0];
3050  /* -------------- */
3051  };
3052  
3053  /* Event Queue Entry */
3054  
3055  struct arbelprm_event_queue_entry_st {	/* Little Endian */
3056      pseudo_bit_t	event_sub_type[0x00008];/* Event Sub Type.
3057                                                   Defined for events which have sub types, zero elsewhere. */
3058      pseudo_bit_t	reserved0[0x00008];
3059      pseudo_bit_t	event_type[0x00008];   /* Event Type */
3060      pseudo_bit_t	reserved1[0x00008];
3061  /* -------------- */
3062      pseudo_bit_t	event_data[6][0x00020];/* Delivers auxilary data to handle event. */
3063  /* -------------- */
3064      pseudo_bit_t	reserved2[0x00007];
3065      pseudo_bit_t	owner[0x00001];        /* Owner of the entry
3066                                                   0 SW
3067                                                   1 HW */
3068      pseudo_bit_t	reserved3[0x00018];
3069  /* -------------- */
3070  };
3071  
3072  /* QP/EE State Transitions Command Parameters */
3073  
3074  struct arbelprm_qp_ee_state_transitions_st {	/* Little Endian */
3075      pseudo_bit_t	opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
3076  /* -------------- */
3077      pseudo_bit_t	reserved0[0x00020];
3078  /* -------------- */
3079      struct arbelprm_queue_pair_ee_context_entry_st	qpc_eec_data;/* QPC/EEC data */
3080  /* -------------- */
3081      pseudo_bit_t	reserved1[0x009c0];
3082  /* -------------- */
3083  };
3084  
3085  /* Completion Queue Entry Format */
3086  
3087  struct arbelprm_completion_queue_entry_st {	/* Little Endian */
3088      pseudo_bit_t	my_qpn[0x00018];       /* Indicates the QP for which completion is being reported */
3089      pseudo_bit_t	reserved0[0x00004];
3090      pseudo_bit_t	ver[0x00004];          /* CQE version.
3091                                                   0 for InfiniHost-III-EX */
3092  /* -------------- */
3093      pseudo_bit_t	my_ee[0x00018];        /* EE context (for RD only).
3094                                                   Invalid for Bind and Nop operation on RD.
3095                                                   For non RD services this filed reports the CQE timestamp. The Timestamp is a free running counter that is incremented every TimeStampGranularity tick. The counter rolls-over when it reaches saturation. TimeStampGranularity is configured in the INIT_HCA command. This feature is currently not supported.
3096                                                    */
3097      pseudo_bit_t	checksum_15_8[0x00008];/* Checksum[15:8] - See IPoverIB checksum offloading chapter */
3098  /* -------------- */
3099      pseudo_bit_t	rqpn[0x00018];         /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */
3100      pseudo_bit_t	checksum_7_0[0x00008]; /* Checksum[7:0] - See IPoverIB checksum offloading chapter */
3101  /* -------------- */
3102      pseudo_bit_t	rlid[0x00010];         /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */
3103      pseudo_bit_t	ml_path[0x00007];      /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW.
3104                                                   Valid in responder of UD QP CQE only.
3105                                                   Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */
3106      pseudo_bit_t	g[0x00001];            /* GRH present indicator. Valid in Responder of UD QP CQE only. */
3107      pseudo_bit_t	ipok[0x00001];         /* IP OK - See IPoverIB checksum offloading chapter */
3108      pseudo_bit_t	reserved1[0x00003];
3109      pseudo_bit_t	sl[0x00004];           /* Service Level of the message. Valid in Responder of UD QP CQE only. */
3110  /* -------------- */
3111      pseudo_bit_t	immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only.
3112                                                   If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet.
3113                                                   If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet.
3114                                                   If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived.
3115                                                   If Opcode field indicates that this was send and invalidate, this field contains the key that was invalidated.
3116                                                   For CQE of send queue of the reliable connection service (but send and invalide), bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message. */
3117  /* -------------- */
3118      pseudo_bit_t	byte_cnt[0x00020];     /* Byte count of data actually transferred (valid for receive queue completions only) */
3119  /* -------------- */
3120      pseudo_bit_t	reserved2[0x00006];
3121      pseudo_bit_t	wqe_adr[0x0001a];      /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
3122  /* -------------- */
3123      pseudo_bit_t	reserved3[0x00007];
3124      pseudo_bit_t	owner[0x00001];        /* Owner field. Zero value of this field means SW ownership of CQE. */
3125      pseudo_bit_t	reserved4[0x0000f];
3126      pseudo_bit_t	s[0x00001];            /* If set, completion is reported for Send queue, if cleared - receive queue. */
3127      pseudo_bit_t	opcode[0x00008];       /* The opcode of WQE completion is reported for.
3128                                                   For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field.
3129                                                   For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field.
3130                                                   For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only)
3131  
3132                                                   The following values are reported in case of completion with error:
3133                                                   0xFE - For completion with error on Receive Queues
3134                                                   0xFF - For completion with error on Send Queues */
3135  /* -------------- */
3136  };
3137  
3138  /*  */
3139  
3140  struct arbelprm_ecc_detect_event_data_st {	/* Little Endian */
3141      pseudo_bit_t	reserved0[0x00080];
3142  /* -------------- */
3143      pseudo_bit_t	cause_lsb[0x00001];
3144      pseudo_bit_t	reserved1[0x00002];
3145      pseudo_bit_t	cause_msb[0x00001];
3146      pseudo_bit_t	reserved2[0x00002];
3147      pseudo_bit_t	err_rmw[0x00001];
3148      pseudo_bit_t	err_src_id[0x00003];
3149      pseudo_bit_t	err_da[0x00002];
3150      pseudo_bit_t	err_ba[0x00002];
3151      pseudo_bit_t	reserved3[0x00011];
3152      pseudo_bit_t	overflow[0x00001];
3153  /* -------------- */
3154      pseudo_bit_t	err_ra[0x00010];
3155      pseudo_bit_t	err_ca[0x00010];
3156  /* -------------- */
3157  };
3158  
3159  /* Event_data Field - ECC Detection Event */
3160  
3161  struct arbelprm_scrubbing_event_st {	/* Little Endian */
3162      pseudo_bit_t	reserved0[0x00080];
3163  /* -------------- */
3164      pseudo_bit_t	cause_lsb[0x00001];    /* data integrity error cause:
3165                                                   single ECC error in the 64bit lsb data, on the rise edge of the clock */
3166      pseudo_bit_t	reserved1[0x00002];
3167      pseudo_bit_t	cause_msb[0x00001];    /* data integrity error cause:
3168                                                   single ECC error in the 64bit msb data, on the fall edge of the clock */
3169      pseudo_bit_t	reserved2[0x00002];
3170      pseudo_bit_t	err_rmw[0x00001];      /* transaction type:
3171                                                   0 - read
3172                                                   1 - read/modify/write */
3173      pseudo_bit_t	err_src_id[0x00003];   /* source of the transaction: 0x4 - PCI, other - internal or IB */
3174      pseudo_bit_t	err_da[0x00002];       /* Error DIMM address */
3175      pseudo_bit_t	err_ba[0x00002];       /* Error bank address */
3176      pseudo_bit_t	reserved3[0x00011];
3177      pseudo_bit_t	overflow[0x00001];     /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */
3178  /* -------------- */
3179      pseudo_bit_t	err_ra[0x00010];       /* Error row address */
3180      pseudo_bit_t	err_ca[0x00010];       /* Error column address */
3181  /* -------------- */
3182  };
3183  
3184  /* Miscellaneous Counters */
3185  
3186  struct arbelprm_misc_counters_st {	/* Little Endian */
3187      pseudo_bit_t	ddr_scan_cnt[0x00020]; /* Number of times whole of LAM was scanned */
3188  /* -------------- */
3189      pseudo_bit_t	reserved0[0x007e0];
3190  /* -------------- */
3191  };
3192  
3193  /* LAM_EN Output Parameter */
3194  
3195  struct arbelprm_lam_en_out_param_st {	/* Little Endian */
3196      pseudo_bit_t	reserved0[0x00040];
3197  /* -------------- */
3198  };
3199  
3200  /* Extended_Completion_Queue_Entry */
3201  
3202  struct arbelprm_extended_completion_queue_entry_st {	/* Little Endian */
3203      pseudo_bit_t	reserved0[0x00020];
3204  /* -------------- */
3205  };
3206  
3207  /*  */
3208  
3209  struct arbelprm_eq_cmd_doorbell_st {	/* Little Endian */
3210      pseudo_bit_t	reserved0[0x00020];
3211  /* -------------- */
3212  };
3213  
3214  /* 0 */
3215  
3216  struct arbelprm_arbel_prm_st {	/* Little Endian */
3217      struct arbelprm_completion_queue_entry_st	completion_queue_entry;/* Completion Queue Entry Format */
3218  /* -------------- */
3219      pseudo_bit_t	reserved0[0x7ff00];
3220  /* -------------- */
3221      struct arbelprm_qp_ee_state_transitions_st	qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */
3222  /* -------------- */
3223      pseudo_bit_t	reserved1[0x7f000];
3224  /* -------------- */
3225      struct arbelprm_event_queue_entry_st	event_queue_entry;/* Event Queue Entry */
3226  /* -------------- */
3227      pseudo_bit_t	reserved2[0x7ff00];
3228  /* -------------- */
3229      struct arbelprm_completion_event_st	completion_event;/* Event_data Field - Completion Event */
3230  /* -------------- */
3231      pseudo_bit_t	reserved3[0x7ff40];
3232  /* -------------- */
3233      struct arbelprm_completion_queue_error_st	completion_queue_error;/* Event_data Field - Completion Queue Error */
3234  /* -------------- */
3235      pseudo_bit_t	reserved4[0x7ff40];
3236  /* -------------- */
3237      struct arbelprm_port_state_change_st	port_state_change;/* Event_data Field - Port State Change */
3238  /* -------------- */
3239      pseudo_bit_t	reserved5[0x7ff40];
3240  /* -------------- */
3241      struct arbelprm_wqe_segment_st	wqe_segment;/* WQE segments format */
3242  /* -------------- */
3243      pseudo_bit_t	reserved6[0x7f000];
3244  /* -------------- */
3245      struct arbelprm_page_fault_event_data_st	page_fault_event_data;/* Event_data Field - Page Faults */
3246  /* -------------- */
3247      pseudo_bit_t	reserved7[0x7ff40];
3248  /* -------------- */
3249      struct arbelprm_performance_monitor_event_st	performance_monitor_event;/* Event Data Field - Performance Monitor */
3250  /* -------------- */
3251      pseudo_bit_t	reserved8[0xfff20];
3252  /* -------------- */
3253      struct arbelprm_mt25208_type0_st	mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */
3254  /* -------------- */
3255      pseudo_bit_t	reserved9[0x7f000];
3256  /* -------------- */
3257      struct arbelprm_qp_ee_event_st	qp_ee_event;/* Event_data Field - QP/EE Events */
3258  /* -------------- */
3259      pseudo_bit_t	reserved10[0x00040];
3260  /* -------------- */
3261      struct arbelprm_gpio_event_data_st	gpio_event_data;
3262  /* -------------- */
3263      pseudo_bit_t	reserved11[0x7fe40];
3264  /* -------------- */
3265      struct arbelprm_ud_address_vector_st	ud_address_vector;/* UD Address Vector */
3266  /* -------------- */
3267      pseudo_bit_t	reserved12[0x7ff00];
3268  /* -------------- */
3269      struct arbelprm_queue_pair_ee_context_entry_st	queue_pair_ee_context_entry;/* QP and EE Context Entry */
3270  /* -------------- */
3271      pseudo_bit_t	reserved13[0x7fa00];
3272  /* -------------- */
3273      struct arbelprm_address_path_st	address_path;/* Address Path */
3274  /* -------------- */
3275      pseudo_bit_t	reserved14[0x7ff00];
3276  /* -------------- */
3277      struct arbelprm_completion_queue_context_st	completion_queue_context;/* Completion Queue Context Table Entry */
3278  /* -------------- */
3279      pseudo_bit_t	reserved15[0x7fe00];
3280  /* -------------- */
3281      struct arbelprm_mpt_st	mpt;         /* Memory Protection Table (MPT) Entry */
3282  /* -------------- */
3283      pseudo_bit_t	reserved16[0x7fe00];
3284  /* -------------- */
3285      struct arbelprm_mtt_st	mtt;         /* Memory Translation Table (MTT) Entry */
3286  /* -------------- */
3287      pseudo_bit_t	reserved17[0x7ffc0];
3288  /* -------------- */
3289      struct arbelprm_eqc_st	eqc;         /* Event Queue Context Table Entry */
3290  /* -------------- */
3291      pseudo_bit_t	reserved18[0x7fe00];
3292  /* -------------- */
3293      struct arbelprm_performance_monitors_st	performance_monitors;/* Performance Monitors */
3294  /* -------------- */
3295      pseudo_bit_t	reserved19[0x7ff80];
3296  /* -------------- */
3297      struct arbelprm_hca_command_register_st	hca_command_register;/* HCA Command Register (HCR) */
3298  /* -------------- */
3299      pseudo_bit_t	reserved20[0xfff20];
3300  /* -------------- */
3301      struct arbelprm_init_hca_st	init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */
3302  /* -------------- */
3303      pseudo_bit_t	reserved21[0x7f000];
3304  /* -------------- */
3305      struct arbelprm_qpcbaseaddr_st	qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */
3306  /* -------------- */
3307      pseudo_bit_t	reserved22[0x7fc00];
3308  /* -------------- */
3309      struct arbelprm_udavtable_memory_parameters_st	udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */
3310  /* -------------- */
3311      pseudo_bit_t	reserved23[0x7ffc0];
3312  /* -------------- */
3313      struct arbelprm_multicastparam_st	multicastparam;/* Multicast Support Parameters */
3314  /* -------------- */
3315      pseudo_bit_t	reserved24[0x7ff00];
3316  /* -------------- */
3317      struct arbelprm_tptparams_st	tptparams;/* Translation and Protection Tables Parameters */
3318  /* -------------- */
3319      pseudo_bit_t	reserved25[0x7ff00];
3320  /* -------------- */
3321      struct arbelprm_enable_lam_st	enable_lam;/* ENABLE_LAM Parameters Block */
3322  /* -------------- */
3323      struct arbelprm_access_lam_st	access_lam;
3324  /* -------------- */
3325      pseudo_bit_t	reserved26[0x7f700];
3326  /* -------------- */
3327      struct arbelprm_dimminfo_st	dimminfo;/* Logical DIMM Information */
3328  /* -------------- */
3329      pseudo_bit_t	reserved27[0x7ff00];
3330  /* -------------- */
3331      struct arbelprm_query_fw_st	query_fw;/* QUERY_FW Parameters Block */
3332  /* -------------- */
3333      pseudo_bit_t	reserved28[0x7f800];
3334  /* -------------- */
3335      struct arbelprm_query_adapter_st	query_adapter;/* QUERY_ADAPTER Parameters Block */
3336  /* -------------- */
3337      pseudo_bit_t	reserved29[0x7f800];
3338  /* -------------- */
3339      struct arbelprm_query_dev_lim_st	query_dev_lim;/* Query Device Limitations */
3340  /* -------------- */
3341      pseudo_bit_t	reserved30[0x7f800];
3342  /* -------------- */
3343      struct arbelprm_uar_params_st	uar_params;/* UAR Parameters */
3344  /* -------------- */
3345      pseudo_bit_t	reserved31[0x7ff00];
3346  /* -------------- */
3347      struct arbelprm_init_ib_st	init_ib; /* INIT_IB Parameters */
3348  /* -------------- */
3349      pseudo_bit_t	reserved32[0x7f800];
3350  /* -------------- */
3351      struct arbelprm_mgm_entry_st	mgm_entry;/* Multicast Group Member */
3352  /* -------------- */
3353      pseudo_bit_t	reserved33[0x7fe00];
3354  /* -------------- */
3355      struct arbelprm_set_ib_st	set_ib;   /* SET_IB Parameters */
3356  /* -------------- */
3357      pseudo_bit_t	reserved34[0x7fe00];
3358  /* -------------- */
3359      struct arbelprm_rd_send_doorbell_st	rd_send_doorbell;/* RD-send doorbell */
3360  /* -------------- */
3361      pseudo_bit_t	reserved35[0x7ff80];
3362  /* -------------- */
3363      struct arbelprm_send_doorbell_st	send_doorbell;/* Send doorbell */
3364  /* -------------- */
3365      pseudo_bit_t	reserved36[0x7ffc0];
3366  /* -------------- */
3367      struct arbelprm_receive_doorbell_st	receive_doorbell;/* Receive doorbell */
3368  /* -------------- */
3369      pseudo_bit_t	reserved37[0x7ffc0];
3370  /* -------------- */
3371      struct arbelprm_cq_cmd_doorbell_st	cq_cmd_doorbell;/* CQ Doorbell */
3372  /* -------------- */
3373      pseudo_bit_t	reserved38[0xfffc0];
3374  /* -------------- */
3375      struct arbelprm_uar_st	uar;         /* User Access Region */
3376  /* -------------- */
3377      pseudo_bit_t	reserved39[0x7c000];
3378  /* -------------- */
3379      struct arbelprm_mgmqp_st	mgmqp;     /* Multicast Group Member QP */
3380  /* -------------- */
3381      pseudo_bit_t	reserved40[0x7ffe0];
3382  /* -------------- */
3383      struct arbelprm_query_debug_msg_st	query_debug_msg;/* Query Debug Message */
3384  /* -------------- */
3385      pseudo_bit_t	reserved41[0x7f800];
3386  /* -------------- */
3387      struct arbelprm_mad_ifc_st	mad_ifc; /* MAD_IFC Input Mailbox */
3388  /* -------------- */
3389      pseudo_bit_t	reserved42[0x00900];
3390  /* -------------- */
3391      struct arbelprm_mad_ifc_input_modifier_st	mad_ifc_input_modifier;/* MAD_IFC Input Modifier */
3392  /* -------------- */
3393      pseudo_bit_t	reserved43[0x7e6e0];
3394  /* -------------- */
3395      struct arbelprm_resize_cq_st	resize_cq;/* Resize CQ Input Mailbox */
3396  /* -------------- */
3397      pseudo_bit_t	reserved44[0x7fe00];
3398  /* -------------- */
3399      struct arbelprm_completion_with_error_st	completion_with_error;/* Completion with Error CQE */
3400  /* -------------- */
3401      pseudo_bit_t	reserved45[0x7ff00];
3402  /* -------------- */
3403      struct arbelprm_hcr_completion_event_st	hcr_completion_event;/* Event_data Field - HCR Completion Event */
3404  /* -------------- */
3405      pseudo_bit_t	reserved46[0x7ff40];
3406  /* -------------- */
3407      struct arbelprm_transport_and_ci_error_counters_st	transport_and_ci_error_counters;/* Transport and CI Error Counters */
3408  /* -------------- */
3409      pseudo_bit_t	reserved47[0x7f000];
3410  /* -------------- */
3411      struct arbelprm_performance_counters_st	performance_counters;/* Performance Counters */
3412  /* -------------- */
3413      pseudo_bit_t	reserved48[0x9ff800];
3414  /* -------------- */
3415      struct arbelprm_fast_registration_segment_st	fast_registration_segment;/* Fast Registration Segment */
3416  /* -------------- */
3417      pseudo_bit_t	reserved49[0x7ff00];
3418  /* -------------- */
3419      struct arbelprm_pbl_st	pbl;         /* Physical Buffer List */
3420  /* -------------- */
3421      pseudo_bit_t	reserved50[0x7ff00];
3422  /* -------------- */
3423      struct arbelprm_srq_context_st	srq_context;/* SRQ Context */
3424  /* -------------- */
3425      pseudo_bit_t	reserved51[0x7fe80];
3426  /* -------------- */
3427      struct arbelprm_mod_stat_cfg_st	mod_stat_cfg;/* MOD_STAT_CFG */
3428  /* -------------- */
3429      pseudo_bit_t	reserved52[0x7f800];
3430  /* -------------- */
3431      struct arbelprm_virtual_physical_mapping_st	virtual_physical_mapping;/* Virtual and Physical Mapping */
3432  /* -------------- */
3433      pseudo_bit_t	reserved53[0x7ff80];
3434  /* -------------- */
3435      struct arbelprm_cq_ci_db_record_st	cq_ci_db_record;/* CQ_CI_DB_Record */
3436  /* -------------- */
3437      pseudo_bit_t	reserved54[0x7ffc0];
3438  /* -------------- */
3439      struct arbelprm_cq_arm_db_record_st	cq_arm_db_record;/* CQ_ARM_DB_Record */
3440  /* -------------- */
3441      pseudo_bit_t	reserved55[0x7ffc0];
3442  /* -------------- */
3443      struct arbelprm_qp_db_record_st	qp_db_record;/* QP_DB_Record */
3444  /* -------------- */
3445      pseudo_bit_t	reserved56[0x1fffc0];
3446  /* -------------- */
3447      struct arbelprm_configuration_registers_st	configuration_registers;/* InfiniHost III EX Configuration Registers */
3448  /* -------------- */
3449      struct arbelprm_eq_set_ci_table_st	eq_set_ci_table;/* EQ Set CI DBs Table */
3450  /* -------------- */
3451      pseudo_bit_t	reserved57[0x01000];
3452  /* -------------- */
3453      struct arbelprm_eq_arm_db_region_st	eq_arm_db_region;/* EQ Arm Doorbell Region */
3454  /* -------------- */
3455      pseudo_bit_t	reserved58[0x00fc0];
3456  /* -------------- */
3457      struct arbelprm_clr_int_st	clr_int; /* Clear Interrupt Register */
3458  /* -------------- */
3459      pseudo_bit_t	reserved59[0xffcfc0];
3460  /* -------------- */
3461  };
3462  #endif /* H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H */
3463