/external/libmpeg2/common/armv8/ |
D | impeg2_format_conv.s | 152 mov x16, x6 158 sub x16, x16, #16 159 cmp x16, #15 162 cmp x16, #0 168 sub x20, x16, #16 169 neg x16, x20 170 sub x0, x0, x16 171 sub x3, x3, x16 196 mov x16, x6 207 sub x16, x16, #8 [all …]
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/external/libhevc/common/arm64/ |
D | ihevc_inter_pred_luma_horz_w16out.s | 137 sub x16,x0,#3 //pu1_src - 3 139 add x8,x16,x2 //pu1_src_tmp2_8 = pu1_src + src_strd 193 sub x16,x0,#3 //pu1_src - 3 197 add x16, x16,#8 204 add x8,x16,x2 //pu1_src + src_strd 211 ld1 {v20.2s},[x16],x15 //vector load pu1_src 212 ld1 {v21.2s},[x16],x15 221 ld1 {v20.2s},[x16],x15 222 ld1 {v21.2s},[x16],x15 231 ld1 {v20.2s},[x16],x15 [all …]
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D | ihevc_inter_pred_luma_copy.s | 86 mov x16,x6 //loads wd 90 tst x16,#15 //checks wd for multiples for 4 & 8 92 tst x16,#7 //checks wd for multiples for 4 & 8 94 sub x15,x16,#4 97 subs x8,x16,#0 //checks wd == 0 132 sub x15,x16,#8 135 subs x8,x16,#0 //checks wd 165 sub x15,x16,#16 168 subs x8,x16,#0 //checks wd
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/external/boringssl/ios-aarch64/crypto/fipsmodule/ |
D | sha512-armv8.S | 78 ror x16,x24,#14 86 eor x16,x16,x6,ror#18 // Sigma1(e) 90 add x27,x27,x16 // h+=Sigma1(e) 103 ror x16,x23,#14 111 eor x16,x16,x7,ror#18 // Sigma1(e) 115 add x26,x26,x16 // h+=Sigma1(e) 127 ror x16,x22,#14 135 eor x16,x16,x8,ror#18 // Sigma1(e) 139 add x25,x25,x16 // h+=Sigma1(e) 152 ror x16,x21,#14 [all …]
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D | armv8-mont.S | 38 mul x16,x14,x15 // np[1]*m1 61 adds x12,x16,x13 67 mul x16,x14,x15 // np[j]*m1 78 adds x12,x16,x13 109 mul x16,x14,x15 // np[1]*m1 123 adds x12,x16,x13 132 mul x16,x14,x15 // np[j]*m1 145 adds x12,x16,x13 295 mul x16,x9,x6 301 adcs x22,x22,x16 [all …]
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/external/boringssl/linux-aarch64/crypto/fipsmodule/ |
D | sha512-armv8.S | 79 ror x16,x24,#14 87 eor x16,x16,x6,ror#18 // Sigma1(e) 91 add x27,x27,x16 // h+=Sigma1(e) 104 ror x16,x23,#14 112 eor x16,x16,x7,ror#18 // Sigma1(e) 116 add x26,x26,x16 // h+=Sigma1(e) 128 ror x16,x22,#14 136 eor x16,x16,x8,ror#18 // Sigma1(e) 140 add x25,x25,x16 // h+=Sigma1(e) 153 ror x16,x21,#14 [all …]
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D | armv8-mont.S | 39 mul x16,x14,x15 // np[1]*m1 62 adds x12,x16,x13 68 mul x16,x14,x15 // np[j]*m1 79 adds x12,x16,x13 110 mul x16,x14,x15 // np[1]*m1 124 adds x12,x16,x13 133 mul x16,x14,x15 // np[j]*m1 146 adds x12,x16,x13 296 mul x16,x9,x6 302 adcs x22,x22,x16 [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-patchpoint-webkit_jscc.ll | 7 ; CHECK-ENCODING: mov x16, #281470681743360 8 ; CHECK-ENCODING: movk x16, #57005, lsl #16 9 ; CHECK-ENCODING: movk x16, #48879 20 ; CHECK-NEXT: mov x16, #281470681743360 21 ; CHECK: movk x16, #57005, lsl #16 22 ; CHECK: movk x16, #48879 23 ; CHECK-NEXT: blr x16 28 ; FAST-NEXT: mov x16, #281470681743360 29 ; FAST-NEXT: movk x16, #57005, lsl #16 30 ; FAST-NEXT: movk x16, #48879 [all …]
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D | arm64-patchpoint.ll | 9 ; CHECK: mov x16, #244834610708480 10 ; CHECK-NEXT: movk x16, #48879, lsl #16 11 ; CHECK-NEXT: movk x16, #51966 12 ; CHECK-NEXT: blr x16 13 ; CHECK: mov x16, #244834610708480 14 ; CHECK-NEXT: movk x16, #48879, lsl #16 15 ; CHECK-NEXT: movk x16, #51967 16 ; CHECK-NEXT: blr x16
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/external/llvm/test/MC/Disassembler/Sparc/ |
D | sparc-mem.txt | 4 0xd4 0x4e 0x00 0x16 16 0xd4 0x56 0x00 0x16 28 0xd4 0x0e 0x00 0x16 40 0xd4 0x16 0x00 0x16 43 0xd4 0x16 0x20 0x20 52 0xd4 0x06 0x00 0x16 64 0xc5 0x06 0x00 0x16 76 0xc5 0x1e 0x00 0x16 88 0xc9 0x16 0x00 0x16 91 0xc9 0x16 0x20 0x20 [all …]
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/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/math/ec/custom/sec/ |
D | SecP521R1Field.java | 49 int x16 = x[16]; in half() local 50 int c = Nat.shiftDownBit(16, x, x16, z); in half() 51 z[16] = (x16 >>> 1) | (c >>> 23); in half() 136 int x16 = x[16]; in twice() local 137 int c = Nat.shiftUpBit(16, x, x16 << 23, z) | (x16 << 1); in twice() 145 int x16 = x[16], y16 = y[16]; in implMultiply() local 146 zz[32] = Nat.mul31BothAdd(16, x16, y, y16, x, zz, 16) + (x16 * y16); in implMultiply() 153 int x16 = x[16]; in implSquare() local 154 zz[32] = Nat.mulWordAddTo(16, x16 << 1, x, 0, zz, 16) + (x16 * x16); in implSquare()
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D | SecP192K1FieldElement.java | 159 int[] x16 = x2; in sqrt() local 160 SecP192K1Field.squareN(x8, 8, x16); in sqrt() 161 SecP192K1Field.multiply(x16, x8, x16); in sqrt() 163 SecP192K1Field.squareN(x16, 3, x19); in sqrt() 167 SecP192K1Field.multiply(x35, x16, x35); in sqrt() 168 int[] x70 = x16; in sqrt()
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/external/libopus/silk/arm/ |
D | NSQ_del_dec_arm.h | 36 SideInfoIndices *psIndices, const opus_int16 x16[], opus_int8 pulses[], 49 #define silk_NSQ_del_dec(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, \ argument 55 psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, LTPCoef_Q14, \ 67 SideInfoIndices *psIndices, const opus_int16 x16[], opus_int8 pulses[], 78 #define silk_NSQ_del_dec(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, \ argument 83 psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, LTPCoef_Q14, \ 88 #define silk_NSQ_del_dec(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, \ argument 93 silk_NSQ_del_dec_neon(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, \
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/external/deqp/doc/ |
D | gles3-test-case-resolutions.txt | 16 dEQP-GLES3.functional.shaders.keywords.* 2x2 16x16 17 dEQP-GLES3.functional.shaders.qualification_order.* 2x2 16x16 34 dEQP-GLES3.functional.shaders.fragdata.* 16x16 32x32 35 dEQP-GLES3.functional.shaders.random.* 16x16 64x64 48 dEQP-GLES3.functional.texture.swizzle.* 16x16 64x64 66 dEQP-GLES3.functional.ubo.* 16x16 32x32 67 dEQP-GLES3.functional.uniform_api.* 16x16 32x32 68 dEQP-GLES3.functional.attribute_location.* 16x16 32x32 78 dEQP-GLES3.functional.transform_feedback.* 16x16 64x64 79 dEQP-GLES3.functional.fence_sync.* 16x16 64x64 [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
D | MBlazeInstrFPU.td | 93 def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIC_FPU>; 94 def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIC_FPU>; 95 def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIC_FPU>; 96 def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIC_FPUd>; 108 def FLT : ArithIF<0x16, 0x280, "flt ", IIC_FPUf>; 109 def FINT : ArithFI<0x16, 0x300, "fint ", IIC_FPUi>; 110 def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIC_FPUs>; 114 def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIC_FPUc>; 115 def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIC_FPUc>; 116 def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIC_FPUc>; [all …]
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | vop1.txt | 135 # CHECK: v_cvt_f32_f16_e32 v123, s55 ; encoding: [0x37,0x16,0xf6,0x7e] 136 0x37 0x16 0xf6 0x7e 165 # CHECK: v_rcp_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x4a,0xbc,0x7f] 166 0x16 0x4a 0xbc 0x7f 168 # CHECK: v_rsq_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x4c,0xbc,0x7f] 169 0x16 0x4c 0xbc 0x7f 171 # CHECK: v_sqrt_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x50,0xbc,0x7f] 172 0x16 0x50 0xbc 0x7f 174 # CHECK: v_frexp_mant_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x62,0xbc,0x7f] 175 0x16 0x62 0xbc 0x7f [all …]
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D | vop3_vi.txt | 192 …4 v[24:25], vcc, v[22:23], v[22:23], v[20:21] ; encoding: [0x18,0x6a,0xe1,0xd1,0x16,0x2d,0x52,0x04] 193 0x18 0x6a 0xe1 0xd1 0x16 0x2d 0x52 0x04 195 …4:25], s[10:11], v[22:23], v[20:21], v[20:21] ; encoding: [0x18,0x0a,0xe1,0xd1,0x16,0x29,0x52,0x04] 196 0x18 0x0a 0xe1 0xd1 0x16 0x29 0x52 0x04 198 # VI: v_div_scale_f32 v24, vcc, v22, v22, v20 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0x52,0x0… 199 0x18 0x6a 0xe0 0xd1 0x16 0x2d 0x52 0x04 204 # VI: v_div_scale_f32 v24, s[10:11], v22, v22, v20 ; encoding: [0x18,0x0a,0xe0,0xd1,0x16,0x2d,0x5… 205 0x18 0x0a 0xe0 0xd1 0x16 0x2d 0x52 0x04 207 # VI: v_div_scale_f32 v24, vcc, v22, 1.0, v22 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0xe5,0x59,0x0… 208 0x18 0x6a 0xe0 0xd1 0x16 0xe5 0x59 0x04 [all …]
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/external/swiftshader/third_party/LLVM/test/Analysis/ScalarEvolution/ |
D | 2008-08-04-IVOverflow.ll | 11 add i16 %0, %x16.0 17 %x16.0 = phi i16 [ 0, %entry ], [ %1, %bb ] 22 zext i16 %x16.0 to i32
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/external/llvm/test/Analysis/ScalarEvolution/ |
D | 2008-08-04-IVOverflow.ll | 11 add i16 %0, %x16.0 17 %x16.0 = phi i16 [ 0, %entry ], [ %1, %bb ] 22 zext i16 %x16.0 to i32
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/external/vixl/test/test-trace-reference/ |
D | log-regs | 17 # x16: 0x1000010001001010 79 # x16: 0x0000013000130013 80 # x16: 0x00000000e963b635 102 # x16: 0xfffffecf168f49d9 120 # x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~ 210 # x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~ 242 # x16: 0x0000000000000083 255 # x16: 0x0000000000000085 267 # x16: 0x000000007bffffff 278 # x16: 0x000000000000000c [all …]
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/external/sonivox/jet_tools/JetCreator/ |
D | img_Open.py | 36 \x9f}\x161\xfe;\xf9\x86\xc8.\x17\x81\xd7\x1f\xfexy\\@\xbb\xdd\x16\xae\xeb\ 39 \xe5\x16\x16\x16\xd8\xde\xde\xe6\xd4\xa9St:\x1dZ!|\xa7<\x8b\xebG\xacnx\x07\ 50 \x10B\xb0\xd3\xd1\x94\x8f\x14\xe8%\x06\xa5\xf4X\x84\x93\x16\xdfp\x1f\xa5\xcd\ 52 \x16\xe6\xde\xc3\x0f\x93At}B\xdd_\x07z\x7f\xae\x87\xa7c\x90\xa1q\x08\xb1w\ 56 \x16/HH\xf6\xa7`\x14\x93\xae\\\x03\xdf\x04\x9b\xb0`\xf3\xe5\xae4\xda|\xd2\ 61 \xf4b5>\xd2\x9bx&\x90\xa6\xfd\x86j\xb5\x16\x06\xbb[?\x07\xde\x03\xfc\x94\x80\
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/external/libopus/silk/ |
D | main.h | 253 …const opus_int16 x16[], /* I Input … 268 #define silk_NSQ(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, LTPCoef_Q14, AR_Q13, \ argument 270 … ((void)(arch),silk_NSQ_c(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, LTPCoef_Q14, AR_Q13, \ 279 …const opus_int16 x16[], /* I Input … 294 #define silk_NSQ_del_dec(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, LTPCoef_Q14, AR_Q13, \ argument 296 …((void)(arch),silk_NSQ_del_dec_c(psEncC, NSQ, psIndices, x16, pulses, PredCoef_Q12, LTPCoef_Q14, A…
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/external/libopus/silk/float/ |
D | wrappers_FLP.c | 106 opus_int16 x16[ MAX_FRAME_LENGTH ]; in silk_NSQ_wrapper_FLP() local 159 x16[ i ] = silk_float2int( x[ i ] ); in silk_NSQ_wrapper_FLP() 164 … silk_NSQ_del_dec( &psEnc->sCmn, psNSQ, psIndices, x16, pulses, PredCoef_Q12[ 0 ], LTPCoef_Q14, in silk_NSQ_wrapper_FLP() 167 silk_NSQ( &psEnc->sCmn, psNSQ, psIndices, x16, pulses, PredCoef_Q12[ 0 ], LTPCoef_Q14, in silk_NSQ_wrapper_FLP()
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/external/wpa_supplicant_8/wpa_supplicant/wpa_gui-qt4/icons/ |
D | Makefile | 4 SIZES := 16x16 22x22 32x32 48x48 64x64 128x128 19 convert hicolor/16x16/apps/$(@:.xpm=.png) pixmaps/$(@:.xpm=-16.xpm)
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/external/llvm/test/MC/AArch64/ |
D | trace-regs.s | 44 mrs x16, trceventctl1r 54 mrs x16, trcvissctlr 426 msr trceventctl0r, x16 444 msr trcseqevr2, x16 445 msr trcseqrstevr, x16 455 msr trccntctlr3, x16 568 msr trcdvcmr5, x16
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