| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_isa.c | 560 unsigned opc; in r600_isa_init() local
573 unsigned opc = op->opcode[isa->hw_class]; in r600_isa_init() local
581 unsigned opc = op->opcode[isa->hw_class]; in r600_isa_init() local
|
| /external/wpa_supplicant_8/src/crypto/ |
| D | milenage.c | 36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1()
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345()
173 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k, in milenage_generate()
208 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts, in milenage_auts()
235 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres, u8 *kc) in gsm_milenage()
270 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand, in milenage_check()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUInstrInfo.cpp | 33 unsigned opc = I->getOpcode(); in isUncondBranch() local
42 unsigned opc = I->getOpcode(); in isCondBranch() local
145 unsigned opc; in storeRegToStackSlot() local
180 unsigned opc; in loadRegFromStackSlot() local
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_disasm.c | 38 uint32_t opc : 6; member
459 #define OPC(opc) [INST_OPCODE_##opc] = {#opc, print_opc_default} argument
460 #define OPC_MOV(opc) [INST_OPCODE_##opc] = {#opc, print_opc_mov} argument
461 #define OPC_TEX(opc) [INST_OPCODE_##opc] = {#opc, print_opc_tex} argument
462 #define OPC_IMM(opc) [INST_OPCODE_##opc] = {#opc, print_opc_imm} argument
522 const unsigned opc = instr->opc | (instr->opcode_bit6 << 6); in print_instr() local
|
| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| D | fd2_compiler.c | 737 struct tgsi_full_instruction *inst, unsigned opc) in translate_tex()
833 struct tgsi_full_instruction *inst, unsigned opc) in translate_sge_slt()
878 unsigned opc) in translate_lrp()
918 unsigned opc) in translate_trig()
982 unsigned opc = inst->Instruction.Opcode; in translate_instruction() local
|
| D | disasm-a2xx.c | 129 #define INSTR(opc, num_srcs) [opc] = { num_srcs, #opc } argument
439 #define INSTR(opc, name, fxn) [opc] = { name, fxn } argument
555 #define INSTR(opc, fxn) [opc] = { #opc, fxn } argument
|
| D | instr-a2xx.h | 212 instr_cf_opc_t opc : 4; member
221 instr_cf_opc_t opc : 4; member
234 instr_cf_opc_t opc : 4; member
243 instr_cf_opc_t opc : 4; member
253 instr_cf_opc_t opc : 4; member
312 instr_fetch_opc_t opc : 5; member
346 instr_fetch_opc_t opc : 5; member
381 instr_fetch_opc_t opc : 5; member
|
| D | ir-a2xx.h | 73 instr_fetch_opc_t opc; member
|
| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| D | disasm-a3xx.c | 655 uint16_t opc; member
659 #define OPC(cat, opc, name) [(opc)] = { (cat), (opc), #name, print_instr_cat##cat } argument
832 uint32_t opc = instr_opc(instr); in print_instr() local
|
| D | instr-a3xx.h | 35 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc) argument
212 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS)) argument
213 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1))) argument
312 uint32_t opc : 4; member
418 uint32_t opc : 6; member
478 uint32_t opc : 4; member
535 uint32_t opc : 6; member
584 uint32_t opc : 5; member
666 uint32_t opc : 5; member
710 static inline bool is_mad(opc_t opc) in is_mad()
[all …]
|
| D | ir3.c | 663 opc_t opc, int nreg) in ir3_instr_create2()
672 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc) in ir3_instr_create()
|
| D | ir3.h | 133 opc_t opc; member
726 static inline bool ir3_cat2_int(opc_t opc) in ir3_cat2_int()
768 static inline unsigned ir3_cat2_absneg(opc_t opc) in ir3_cat2_absneg()
828 static inline unsigned ir3_cat3_absneg(opc_t opc) in ir3_cat3_absneg()
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_emit_nvc0.cpp | 377 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc) in emitForm_A()
422 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc) in emitForm_B()
451 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred) in emitForm_S()
1839 uint32_t opc; in emitSTORE() local
1886 uint32_t opc; in emitLOAD() local
2015 uint64_t opc; in emitMOV() local
2223 uint64_t opc; in emitSUCalc() local
2478 uint64_t opc = 0x4; in emitVSHL() local
|
| /external/autotest/client/cros/cellular/ |
| D | prologix_scpi_driver_test_noautorun.py | 184 def _get_idns_and_verify(self, instruments, opc=False): argument
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackend.cpp | 241 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 in adjustFixupValue() local
254 unsigned opc = 0; in adjustFixupValue() local
|
| /external/libunwind/include/tdep-ia64/ |
| D | script.h | 36 unsigned int opc; /* see enum ia64_script_insn_opcode */ member
|
| /external/libunwind/src/ia64/ |
| D | Gscript.c | 267 enum ia64_script_insn_opcode opc; in compile_reg() local
521 unsigned long opc, dst; in run_script() local
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeTILEGX_64.c | 524 void insert_nop(tilegx_mnemonic opc, int line) in insert_nop()
566 tilegx_mnemonic opc = inst_buf[0].opcode->can_bundle in assign_pipes() local
744 static sljit_s32 push_4_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int o… in push_4_buffer()
764 static sljit_s32 push_3_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int o… in push_3_buffer()
825 static sljit_s32 push_2_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int o… in push_2_buffer()
870 static sljit_s32 push_0_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int line) in push_0_buffer()
886 static sljit_s32 push_jr_buffer(struct sljit_compiler *compiler, tilegx_mnemonic opc, int op0, int … in push_jr_buffer()
|
| /external/f2fs-tools/tools/sg_write_buffer/include/ |
| D | freebsd_nvme_ioctl.h | 39 uint16_t opc : 8; /* opcode */ member
|
| /external/valgrind/VEX/priv/ |
| D | host_mips_defs.c | 2113 static UChar *mkFormI(UChar * p, UInt opc, UInt rs, UInt rt, UInt imm) in mkFormI()
2131 static UChar *mkFormR(UChar * p, UInt opc, UInt rs, UInt rt, UInt rd, UInt sa, in mkFormR()
3176 UInt opc, sz = i->Min.Load.sz; in emit_MIPSInstr() local
3203 UInt opc, sz = i->Min.Load.sz; in emit_MIPSInstr() local
3233 UInt opc, sz = i->Min.Store.sz; in emit_MIPSInstr() local
3260 UInt opc, sz = i->Min.Store.sz; in emit_MIPSInstr() local
|
| /external/llvm/lib/IR/ |
| D | ConstantsContext.h | 265 CompareConstantExpr(Type *ty, Instruction::OtherOps opc, in CompareConstantExpr()
|
| D | Instruction.cpp | 627 #define HANDLE_INST(num, opc, clas) \ in clone() argument
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackend.cpp | 431 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 in adjustFixupValue() local
446 unsigned opc = 0; in adjustFixupValue() local
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| D | MallocOverflowSecurityChecker.cpp | 83 BinaryOperatorKind opc = binop->getOpcode(); in CheckMallocArgument() local
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonNewValueJump.cpp | 637 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, in runOnMachineFunction() local
|